Alexander Saldanha

30 papers A* 10A 10Misc 2Journal 7Unranked 1

Year	Rank	Type	Title / Venue / Authors
2007	J	`jnl`	FSM Encoding for BDD Representations. Int. J. Appl. Math. Comput. Sci. Wilsin Gosti, Tiziano Villa, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli
2000	Misc	`conf`	Timing Analysis with Implicitly Specified False Paths. VLSI Design Eugene Goldberg, Alexander Saldanha
1999	A	`conf`	A methodology for correct-by-construction latency insensitive design. ICCAD Luca P. Carloni, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli
1999	A	`conf`	Functional timing optimization. ICCAD Alexander Saldanha
1998	—	`conf`	An Exact Input Encoding Algorithm for BDDs Representing FSMs. Great Lakes Symposium on VLSI Wilsin Gosti, Alberto L. Sangiovanni-Vincentelli, Tiziano Villa, Alexander Saldanha
1998	J	`jnl`	Partial-scan delay fault testing of asynchronous circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin
1997	A	`conf`	Approximate timing analysis of combinational circuits under the XBD0 model. ICCAD Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, Robert K. Brayton
1997	A	`conf`	Partial scan delay fault testing of asynchronous circuits. ICCAD Michael Kishinevsky, Alex Kondratyev, Luciano Lavagno, Alexander Saldanha, Alexander Taubin
1997	J	`jnl`	Symbolic two-level minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Tiziano Villa, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1997	A	`conf`	Trace driven logic synthesis - application to power minimization. ICCAD Luca P. Carloni, Patrick C. McGeer, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli
1996	A	`conf`	Compact and complete test set generation for multiple stuck-faults. ICCAD Alok Agrawal, Alexander Saldanha, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
1996	A*	`conf`	Verification of Electronic Systems. DAC Alberto L. Sangiovanni-Vincentelli, Patrick C. McGeer, Alexander Saldanha
1995	J	`jnl`	Delay fault coverage, test set size, and performance trade-offs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1995	A	`conf`	Fast discrete function evaluation using decision diagrams. ICCAD Patrick C. McGeer, Kenneth L. McMillan, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli, Patrick Scaglia
1995	Misc	`conf`	Functional clock schedule optimization. VLSI Design Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1995	A*	`conf`	Supervisory Control of Finite State Machines. CAV Adnan Aziz, Felice Balarin, Robert K. Brayton, Marika Domenica Di Benedetto, Alexander Saldanha
1995	A*	`conf`	Timed Shannon Circuits: A Power-Efficient Design Style and Synthesis Tool. DAC Luciano Lavagno, Patrick C. McGeer, Alexander Saldanha, Alberto L. Sangiovanni-Vincentelli
1994	J	`jnl`	Circuit structure relations to redundancy and delay. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1994	A*	`conf`	Performance Optimization Using Exact Sensitization. DAC Alexander Saldanha, Heather Harkness, Patrick C. McGeer, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1994	J	`jnl`	Satisfaction of input and output encoding constraints. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1993	A*	`conf`	Delay Fault Coverage and Performance Tradeoffs. DAC William K. C. Lam, Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1992	A*	`conf`	Circuit Structure Relations to Redundancy and Delay: The KMS Algorithm Revisited. DAC Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1992	A*	`conf`	Equivalence of Robust Delay-Fault and Single Stuck-Fault Test Generation. DAC Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1991	A*	`conf`	A Framework for Satisfying Input and Output Encoding Constraints. DAC Alexander Saldanha, Tiziano Villa, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1991	J	`jnl`	Is redundancy necessary to reduce delay? IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Kurt Keutzer, Sharad Malik, Alexander Saldanha
1991	A	`conf`	Timing Analysis and Delay-Fault Test Generation using Path-Recursive Functions. ICCAD Patrick C. McGeer, Alexander Saldanha, Paul R. Stephan, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1990	A*	`conf`	Is Redundancy Necessary to Reduce Delay. DAC Kurt Keutzer, Sharad Malik, Alexander Saldanha
1990	A	`conf`	Timing Optimization with Testability Considerations. ICCAD Alexander Saldanha, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli, Kwang-Ting Cheng
1989	A*	`conf`	Multi-level Logic Simplification Using Don't Cares and Filters. DAC Alexander Saldanha, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1988	A	`conf`	PLA optimization using output encoding. ICCAD Alexander Saldanha, Randy H. Katz