Alexander Edward

11 papers C 1Journal 8Unranked 2
YearRankTypeTitle / Venue / Authors
2018 J jnl
A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs.
IEEE J. Solid State Circuits
Carlos Briseno-Vidrios, Dadian Zhou, Suraj Prakash, Qiyuan Liu, Alexander Edward, Eric G. Soenen, Martin Kinyua, José Silva-Martínez
2018 J jnl
A Continuous-Time MASH 1-1-1 Delta-Sigma Modulator With FIR DAC and Encoder-Embedded Loop-Unrolling Quantizer in 40-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst.
Qiyuan Liu, Alexander Edward, Dadian Zhou, José Silva-Martínez
2017 C conf
A 13bit 200MS/S pipeline ADC with current-mode MDACs.
ISCAS
Carlos Briseno-Vidrios, Dadian Zhou, Suraj Prakash, Qiyuan Liu, Alexander Edward, José Silva-Martínez
2017 J jnl
A 43-mW MASH 2-2 CT ΣΔ Modulator Attaining 74.4/75.8/76.8 dB of SNDR/SNR/DR and 50 MHz of BW in 40-nm CMOS.
IEEE J. Solid State Circuits
Alexander Edward, Qiyuan Liu, Carlos Briseno-Vidrios, Martin Kinyua, Eric G. Soenen, Aydin Ilker Karsilayan, José Silva-Martínez
2017 J jnl
A 75-MHz Continuous-Time Sigma-Delta Modulator Employing a Broadband Low-Power Highly Efficient Common-Gate Summing Stage.
IEEE J. Solid State Circuits
Carlos Briseno-Vidrios, Alexander Edward, Ayman Shafik, Samuel Palermo, José Silva-Martínez
2017 J jnl
A Low-Power Digitizer for Back-Illuminated 3-D-Stacked CMOS Image Sensor Readout With Passing Window and Double Auto-Zeroing Techniques.
IEEE J. Solid State Circuits
Qiyuan Liu, Alexander Edward, Martin Kinyua, Eric G. Soenen, José Silva-Martínez
2017 — conf
High-performance continuous-time MASH sigma-delta ADCs for broadband wireless applications.
MWSCAS
Qiyuan Liu, Alexander Edward, Carlos Briseno-Vidrios, Negar Rashidi, José Silva-Martínez
2016 J jnl
A 4 Bit Continuous-Time ΣΔ Modulator With Fully Digital Quantization Noise Reduction Algorithm Employing a 7 Bit Quantizer.
IEEE J. Solid State Circuits
Carlos Briseno-Vidrios, Alexander Edward, Negar Rashidi, José Silva-Martínez
2015 — conf
A 75 MHz BW 68dB DR CT-ΣΔ modulator with single amplifier biquad filter and a broadband low-power common-gate summing technique.
VLSIC
Carlos Briseno-Vidrios, Alexander Edward, Ayman Shafik, Samuel Palermo, José Silva-Martínez
2014 J jnl
General Analysis of Feedback DAC's Clock Jitter in Continuous-Time Sigma-Delta Modulators.
IEEE Trans. Circuits Syst. II Express Briefs
Alexander Edward, José Silva-Martínez
2012 J jnl
An Ultra-Low Voltage Analog Front End for Strain Gauge Sensory System Application in 0.18 µm CMOS.
IEICE Trans. Electron.
Alexander Edward, Pak Kwong Chan