Alex Orailoglu

299 papers A* 17A 53B 6C 28Misc 36Journal 79Unranked 73
YearRankTypeTitle / Venue / Authors
2026 — conf
PrometheusFree: Concurrent Detection of Laser Fault Injection Attacks in Optical Neural Networks.
ASP-DAC
Kota Nishida, Yoshihiro Midoh, Noriyuki Miura, Satoshi Kawakami, Alex Orailoglu, Jun Shiomi
2025 — conf
Boosting Scan Chain Security in a White-box through Restricted Pattern Filtering.
ISVLSI
Leon Li, Alex Orailoglu
2025 — conf
Breaking the One-Shot Barrier: Progressive Error Detection in FSM via Key-Driven Corruption.
ATS
Leon Li, Alex Orailoglu
2025 J jnl
Linear Algorithmic Checksums for Deep-Neural-Network Error Detection: Fundamentals and Recent Advancements.
IEEE Des. Test
Elbruz Ozen, Ozgur Ozerdem, Alex Orailoglu
2025 — conf
White-box logic obfuscation: A Transparent Solution to Hardware Piracy and Reverse Engineering.
ASP-DAC
Leon Li, Alex Orailoglu
2024 A conf
Locked-by-Design: Enhancing White-box Logic Obfuscation with Effective Key Mutation.
ITC
Leon Li, Alex Orailoglu
2024 J jnl
Special Issue on SAMOS 2022.
Int. J. Parallel Program.
Alex Orailoglu, Marc Reichenbach, Matthias Jung
2024 B conf
Transcoders: A Better Alternative To Denoising Autoencoders.
ETS
Pushpak Raj Gautam, Alex Orailoglu
2023 — conf
ClearLock: Deterring Hardware Reverse Engineering Attacks in a White-Box.
ATS
Leon Li, Alex Orailoglu
2023 J jnl
Redundancy Attack: Breaking Logic Locking Through Oracleless Rationality Analysis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Leon Li, Alex Orailoglu
2023 J jnl
Shaping Resilient AI Hardware Through DNN Computational Feature Exploitation.
IEEE Des. Test
Elbruz Ozen, Alex Orailoglu
2023 Misc conf
Thwarting Reverse Engineering Attacks through Keyless Logic Obfuscation.
VTS
Leon Li, Alex Orailoglu
2023 J jnl
Unleashing the Potential of Sparse DNNs Through Synergistic Hardware-Sparsity Co-Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Elbruz Ozen, Alex Orailoglu
2022 J jnl
Architecting Decentralization and Customizability in DNN Accelerators for Hardware Defect Adaptation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Elbruz Ozen, Alex Orailoglu
2022 — ed.
Embedded Computer Systems: Architectures, Modeling, and Simulation - 21st International Conference, SAMOS 2021, Virtual Event, July 4-8, 2021, Proceedings
SAMOS
Alex Orailoglu, Matthias Jung, Marc Reichenbach
2022 — ed.
Embedded Computer Systems: Architectures, Modeling, and Simulation - 22nd International Conference, SAMOS 2022, Samos, Greece, July 3-7, 2022, Proceedings
SAMOS
Alex Orailoglu, Marc Reichenbach, Matthias Jung
2022 J jnl
Guest Editorial: Special Issue on 2020 IEEE International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS 2020).
Int. J. Parallel Program.
Marc Reichenbach, Matthias Jung, Alex Orailoglu
2022 A conf
JANUS-HD: Exploiting FSM Sequentiality and Synthesis Flexibility in Logic Obfuscation to Thwart SAT Attack While Offering Strong Corruption.
DATE
Leon Li, Alex Orailoglu
2021 J jnl
AdaTrust: Combinational Hardware Trojan Detection Through Adaptive Test Pattern Construction.
IEEE Trans. Very Large Scale Integr. Syst.
Chris Nigh, Alex Orailoglu
2021 A conf
Evolving Complementary Sparsity Patterns for Hardware-Friendly Inference of Sparse DNNs.
ICCAD
Elbruz Ozen, Alex Orailoglu
2021 — conf
JANUS: Boosting Logic Obfuscation Scope Through Reconfigurable FSM Synthesis.
HOST
Leon Li, Shuyi Ni, Alex Orailoglu
2021 J jnl
SNR: Squeezing Numerical Range Defuses Bit Error Vulnerability Surface in Deep Neural Networks.
ACM Trans. Embed. Comput. Syst.
Elbruz Ozen, Alex Orailoglu
2020 A conf
A Crowd-Based Explosive Detection System with Two-Level Feedback Sensor Calibration.
ICCAD
Chengmo Yang, Patrick Cronin, Agamyrat Agambayev, Sule Ozev, A. Enis Çetin, Alex Orailoglu
2020 J jnl
Benchmarking at the Frontier of Hardware Security: Lessons from Logic Locking.
CoRR
Benjamin Tan, Ramesh Karri, Nimisha Limaye, Abhrajit Sengupta, Ozgur Sinanoglu, Md. Moshiur Rahman, Swarup Bhunia, Danielle Duvalsaint, Ronald D. Blanton, Amin Rezaei, Yuanqi Shen, Hai Zhou, Leon Li, Alex Orailoglu, Zhaokun Han, Austin Benedetti, Luciano Brignone, Muhammad Yasin, Jeyavijayan Rajendran, Michael Zuzak, Ankur Srivastava, Ujjwal Guin, Chandan Karfa, Kanad Basu, Vivek V. Menon, Matthew French, Peilin Song, Franco Stellari, Gi-Joon Nam, Peter Gadfort, Alric Althoff, Joseph Tostenrude, Saverio Fazzari, Eric Breckenfeld, Kenneth Plaks
2020 J jnl
Boosting Bit-Error Resilience of DNN Accelerators Through Median Feature Selection.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Elbruz Ozen, Alex Orailoglu
2020 — conf
Concurrent Monitoring of Operational Health in Neural Networks Through Balanced Output Partitions.
ASP-DAC
Elbruz Ozen, Alex Orailoglu
2020 — ed.
Embedded Computer Systems: Architectures, Modeling, and Simulation - 20th International Conference, SAMOS 2020, Samos, Greece, July 5-9, 2020, Proceedings
SAMOS
Alex Orailoglu, Matthias Jung, Marc Reichenbach
2020 A conf
Hunting Sybils in Participatory Mobile Consensus-Based Networks.
AsiaCCS
Nickolai Verchok, Alex Orailoglu
2020 A conf
Just Say Zero: Containing Critical Bit-Error Propagation in Deep Neural Networks With Anomalous Feature Suppression.
ICCAD
Elbruz Ozen, Alex Orailoglu
2020 J jnl
Low-Cost Error Detection in Deep Neural Network Accelerators with Linear Algorithmic Checksums.
J. Electron. Test.
Elbruz Ozen, Alex Orailoglu
2020 — conf
Squeezing Correlated Neurons for Resource-Efficient Deep Neural Networks.
ECML/PKDD (2)
Elbruz Ozen, Alex Orailoglu
2020 Misc conf
Taming Combinational Trojan Detection Challenges with Self-Referencing Adaptive Test Patterns.
VTS
Chris Nigh, Alex Orailoglu
2020 A conf
Test Pattern Superposition to Detect Hardware Trojans.
DATE
Chris Nigh, Alex Orailoglu
2019 J jnl
Detecting Gas Vapor Leaks Using Uncalibrated Sensors.
IEEE Access
Diaa Badawi, Tuba Ayhan, Sule Ozev, Chengmo Yang, Alex Orailoglu, Ahmet Enis Çetin
2019 J jnl
Detecting Gas Vapor Leaks Using Uncalibrated Sensors.
CoRR
Diaa Badawi, Tuba Ayhan, Sule Ozev, Chengmo Yang, Alex Orailoglu, A. Enis Çetin
2019 Misc conf
Detecting Gas Vapor Leaks through Uncalibrated Sensor Based CPS.
ICASSP
Diaa Badawi, Sule Ozev, Jennifer Blain Christen, Chengmo Yang, Alex Orailoglu, A. Enis Çetin
2019 A conf
Piercing Logic Locking Keys through Redundancy Identification.
DATE
Leon Li, Alex Orailoglu
2019 — conf
Sanity-Check: Boosting the Reliability of Safety-Critical Deep Neural Network Applications.
ATS
Elbruz Ozen, Alex Orailoglu
2019 Misc conf
Shielding Logic Locking from Redundancy Attacks.
VTS
Leon Li, Alex Orailoglu
2019 — conf
The Return of Power Gating: Smart Leakage Energy Reductions in Modern Out-of-Order Processor Architectures.
ARCS
Elbruz Ozen, Alex Orailoglu
2018 A conf
Variation-Aware Hardware Trojan Detection through Power Side-channel.
ITC
Fakir Sharif Hossain, Michihiro Shintani, Michiko Inoue, Alex Orailoglu
2017 B conf
Detecting hardware Trojans without a Golden IC through clock-tree defined circuit partitions.
ETS
Fakir Sharif Hossain, Tomokazu Yoneda, Michiko Inoue, Alex Orailoglu
2017 — conf
Ensuring system security through proximity based authentication.
ASP-DAC
Joshua Marxen, Alex Orailoglu
2017 — conf
Intra-Die-Variation-Aware Side Channel Analysis for Hardware Trojan Detection.
ATS
Fakir Sharif Hossain, Tomokazu Yoneda, Michihiro Shintani, Michiko Inoue, Alex Orailoglu
2016 J jnl
Aggressive Test Cost Reductions Through Continuous Test Effectiveness Assessment.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Baris Arslan, Alex Orailoglu
2016 J jnl
Power-Aware Delay Test Quality Optimization for Multiple Frequency Domains.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Baris Arslan, Alex Orailoglu
2015 J jnl
Joint Profit and Process Variation Aware High Level Synthesis With Speed Binning.
IEEE Trans. Very Large Scale Integr. Syst.
Mengying Zhao, Alex Orailoglu, Chun Jason Xue
2015 — conf
Mobile Ecosystem Driven Dynamic Pipeline Adaptation for Low Power.
ARCS
Garo Bournoutian, Alex Orailoglu
2015 C conf
Mobile ecosystem driven application-specific low-power control microarchitecture.
ICCD
Garo Bournoutian, Alex Orailoglu
2015 — ed.
VLSI-SoC: At the Crossroads of Emerging Trends - 21st IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2013, Istanbul, Turkey, October 6-9, 2013, Revised and Extended Selected Papers
VLSI-SoC (Selected Papers)
Alex Orailoglu, H. Fatih Ugurdag, Luís Miguel Silveira, Martin Margala, Ricardo Reis
2014 J jnl
Branch Prediction-Directed Dynamic Instruction Cache Locking for Embedded Systems.
ACM Trans. Embed. Comput. Syst.
Keni Qiu, Mengying Zhao, Chun Jason Xue, Alex Orailoglu
2014 J jnl
Examining Timing Path Robustness Under Wide-Bandwidth Power Supply Noise Through Multi-Functional-Cycle Delay Test.
IEEE Trans. Very Large Scale Integr. Syst.
Mingjing Chen, Alex Orailoglu
2014 A conf
On-device objective-C application optimization framework for high-performance mobile processors.
DATE
Garo Bournoutian, Alex Orailoglu
2014 A conf
Sleep-aware variable partitioning for energy-efficient hybrid PRAM and DRAM main memory.
ISLPED
Chenchen Fu, Mengying Zhao, Chun Jason Xue, Alex Orailoglu
2013 C ed.
21st IEEE/IFIP International Conference on VLSI and System-on-Chip, VLSI-SoC 2013, Istanbul, Turkey, October 7-9, 2013
VLSI-SoC
Martin Margala, Ricardo Augusto da Luz Reis, Alex Orailoglu, Luigi Carro, Luís Miguel Silveira, H. Fatih Ugurdag
2013 J jnl
Application-aware adaptive cache architecture for power-sensitive mobile processors.
ACM Trans. Embed. Comput. Syst.
Garo Bournoutian, Alex Orailoglu
2013 B conf
Branch Prediction directed Dynamic instruction Cache Locking for embedded systems.
RTCSA
Keni Qiu, Mengying Zhao, Chun Jason Xue, Alex Orailoglu
2013 — conf
Full exploitation of process variation space for continuous delivery of optimal delay test quality.
ASP-DAC
Baris Arslan, Alex Orailoglu
2013 A conf
Profit maximization through process variation aware high level synthesis with speed binning.
DATE
Mengying Zhao, Alex Orailoglu, Chun Jason Xue
2013 J jnl
Register allocation for embedded systems to simultaneously reduce energy and temperature on registers.
ACM Trans. Embed. Comput. Syst.
Tiantian Liu, Alex Orailoglu, Chun Jason Xue, Minming Li
2013 Misc conf
Towards a cost-effective hardware trojan detection methodology.
VTS
Raymond Paseman, Alex Orailoglu
2013 Misc conf
Tracing the best test mix through multi-variate quality tracking.
VTS
Baris Arslan, Alex Orailoglu
2012 Misc conf
Delay test resource allocation and scheduling for multiple frequency domains.
VTS
Baris Arslan, Alex Orailoglu
2012 Misc conf
Dynamic transient fault detection and recovery for embedded processor datapaths.
CODES+ISSS
Garo Bournoutian, Alex Orailoglu
2012 J jnl
On Diagnosis of Timing Failures in Scan Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Mingjing Chen, Alex Orailoglu
2012 J jnl
Scan Power Reduction for Linear Test Compression Schemes Through Seed Selection.
IEEE Trans. Very Large Scale Integr. Syst.
Mingjing Chen, Alex Orailoglu
2012 Misc conf
Small-delay defects detection under process variation using Inter-Path Correlation.
VTS
Francisco J. Galarza-Medina, Jose Luis Garcia-Gervacio, Víctor H. Champac, Alex Orailoglu
2012 J jnl
Tackling Resource Variations Through Adaptive Multicore Execution Frameworks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Chengmo Yang, Alex Orailoglu
2011 — conf
Adaptive Test Framework for Achieving Target Test Quality at Minimal Cost.
Asian Test Symposium
Baris Arslan, Alex Orailoglu
2011 A conf
Adaptive test optimization through real time learning of test effectiveness.
DATE
Baris Arslan, Alex Orailoglu
2011 A conf
Diagnosing scan chain timing faults through statistical feature analysis of scan images.
DATE
Mingjing Chen, Alex Orailoglu
2011 A* conf
Diagnosing scan clock delay faults through statistical timing pruning.
DAC
Mingjing Chen, Alex Orailoglu
2011 Misc conf
Dynamic, multi-core cache coherence architecture for power-sensitive mobile processors.
CODES+ISSS
Garo Bournoutian, Alex Orailoglu
2011 A conf
Frugal but flexible multicore topologies in support of resource variation-driven adaptivity.
DATE
Chengmo Yang, Alex Orailoglu
2011 J jnl
Full Fault Resilience and Relaxed Synchronization Requirements at the Cache-Memory Interface.
IEEE Trans. Very Large Scale Integr. Syst.
Chengmo Yang, Alex Orailoglu
2011 J jnl
Migration-aware adaptive MPSoC static schedules with dynamic reconfigurability.
J. Parallel Distributed Comput.
Yuping Zhang, Chun Jason Xue, Chengmo Yang, Alex Orailoglu
2011 A conf
Register allocation for simultaneous reduction of energy and peak temperature on registers.
DATE
Tiantian Liu, Alex Orailoglu, Chun Jason Xue, Minming Li
2011 J jnl
Toward Future Systems with Nanoscale Devices: Overcoming the Reliability Challenge.
Computer
Wenjing Rao, Chengmo Yang, Ramesh Karri, Alex Orailoglu
2010 A conf
Cost-effective IR-drop failure identification and yield recovery through a failure-adaptive test scheme.
DATE
Mingjing Chen, Alex Orailoglu
2010 C conf
Delay test quality maximization through process-aware selection of test set size.
ICCD
Baris Arslan, Alex Orailoglu
2010 J jnl
DiSC: A New Diagnosis Method for Multiple Scan Chain Failures.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Sunghoon Chun, Alex Orailoglu
2010 Misc conf
Dynamic, non-linear cache architecture for power-sensitive mobile processors.
CODES+ISSS
Garo Bournoutian, Alex Orailoglu
2010 C conf
Fine-grained adaptive CMP cache sharing through access history exploitation.
VLSI-SoC
Chengmo Yang, Chun Jason Xue, Alex Orailoglu
2010 C conf
Fully adaptive multicore architectures through statically-directed dynamic execution reconfigurations.
VLSI-SoC
Chengmo Yang, Alex Orailoglu
2010 Misc conf
High durability in NAND flash memory through effective page reuse mechanisms.
CODES+ISSS
Kwangyoon Lee, Alex Orailoglu
2010 — conf
Performance and energy efficient cache migrationapproach for thermal management in embedded systems.
ACM Great Lakes Symposium on VLSI
Raid Ayoub, Alex Orailoglu
2010 — ed.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2010, São Paulo, Brazil, September 6-9, 2010
SBCCI
João Antonio Martino, Guido Araujo, Alex Orailoglu, Felipe Klein
2010 J jnl
Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions.
Des. Autom. Embed. Syst.
Garo Bournoutian, Alex Orailoglu
2010 J jnl
Squashing code size in microcoded IPs while delivering high decompression speed.
Des. Autom. Embed. Syst.
Chengmo Yang, Mingjing Chen, Alex Orailoglu
2010 Misc conf
VDDmin test optimization for overscreening minimization through adaptive scan chain masking.
VTS
Mingjing Chen, Alex Orailoglu
2009 — conf
Deflecting crosstalk by routing reconsideration through refined signal correlation estimation.
ACM Great Lakes Symposium on VLSI
Mingjing Chen, Alex Orailoglu
2009 — conf
Filtering Global History: Power and Performance Efficient Branch Predictor.
ASAP
Raid Ayoub, Alex Orailoglu
2009 — conf
Flip-Flop Hardening and Selection for Soft Error and Delay Fault Resilience.
DFT
Mingjing Chen, Alex Orailoglu
2009 J jnl
Guest Editorial Special Section on the IEEE Symposium on Application Specific Processors 2008.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Alex Orailoglu, Laura Pozzi
2009 J jnl
Logic Mapping in Crossbar-Based Nanoarchitectures.
IEEE Des. Test Comput.
Wenjing Rao, Alex Orailoglu, Ramesh Karri
2009 J jnl
Low-Power Scan Testing for Test Data Compression Using a Routing-Driven Scan Architecture.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Dong Xiang, Dianwei Hu, Qiang Xu, Alex Orailoglu
2009 A conf
Making DNA self-assembly error-proof: Attaining small growth error rates through embedded information redundancy.
DATE
Saturnino Garcia, Alex Orailoglu
2009 A conf
Processor reliability enhancement through compiler-directed register file peak temperature reduction.
DSN
Chengmo Yang, Alex Orailoglu
2009 Misc conf
Reducing impact of cache miss stalls in embedded systems by extracting guaranteed independent instructions.
CASES
Garo Bournoutian, Alex Orailoglu
2009 J jnl
Scan Cell Positioning for Boosting the Compression of Fan-Out Networks.
J. Comput. Sci. Technol.
Ozgur Sinanoglu, Mohammed Al-Mulla, Noora A. Shunaiber, Alex Orailoglu
2009 A conf
Scan power reduction in linear test data compression scheme.
ICCAD
Mingjing Chen, Alex Orailoglu
2009 Misc conf
Squashing microcode stores to size in embedded systems while delivering rapid microcode accesses.
CODES+ISSS
Chengmo Yang, Mingjing Chen, Alex Orailoglu
2009 A conf
Towards no-cost adaptive MPSoC static schedules through exploitation of logical-to-physical core mapping latitude.
DATE
Chengmo Yang, Alex Orailoglu
2008 Misc conf
A light-weight cache-based fault detection and checkpointing scheme for MPSoCs enabling relaxed execution synchronization.
CASES
Chengmo Yang, Alex Orailoglu
2008 — conf
Application Specific Low Latency Instruction Cache for NAND Flash Memory Based Embedded Systems.
SASP
Kwangyoon Lee, Alex Orailoglu
2008 Misc conf
Application specific non-volatile primary memory for embedded systems.
CODES+ISSS
Kwangyoon Lee, Alex Orailoglu
2008 — conf
Locality aware redundancy allocation in nanoelectronic systems.
NANOARCH
Wenjing Rao, Alex Orailoglu, Keith Marzullo
2008 A* conf
Miss reduction in embedded processors through dynamic, power-friendly cache design.
DAC
Garo Bournoutian, Alex Orailoglu
2008 — conf
Online test and fault-tolerance for nanoelectronic programmable logic arrays.
NANOARCH
Saturnino Garcia, Alex Orailoglu
2008 J jnl
Scheduling Power-Constrained Tests through the SoC Functional Bus.
IEICE Trans. Inf. Syst.
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara
2008 C conf
Test cost minimization through adaptive test development.
ICCD
Mingjing Chen, Alex Orailoglu
2008 A conf
Towards fault tolerant parallel prefix adders in nanoelectronic systems.
DATE
Wenjing Rao, Alex Orailoglu
2007 J jnl
Architectures for Silicon Nanoelectronics and Beyond.
Computer
R. Iris Bahar, Dan W. Hammerstrom, Justin E. Harlow III, William H. Joyner Jr., Clifford Lau, Diana Marculescu, Alex Orailoglu, Massoud Pedram
2007 C conf
Circuit-level mismatch modelling and yield optimization for CMOS analog circuits.
ICCD
Mingjing Chen, Alex Orailoglu
2007 — conf
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses.
ASP-DAC
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara
2007 — conf
Design automation for hybrid CMOS-nonoelectronics crossbars.
NANOARCH
Kyosun Kim, Ramesh Karri, Alex Orailoglu
2007 J jnl
Dynamic Tag Reduction for Low-Power Caches in Embedded Systems with Virtual Memory.
Int. J. Parallel Program.
Peter Petrov, Alex Orailoglu
2007 A conf
Fault Tolerant Approaches to Nanoelectronic Programmable Logic Arrays.
DSN
Wenjing Rao, Alex Orailoglu, Ramesh Karri
2007 J jnl
Guest Editorial.
IEEE Trans. Circuits Syst. I Regul. Pap.
Clifford Lau, Alex Orailoglu, Kaushik Roy
2007 — conf
Improving Circuit Robustness with Cost-Effective Soft-Error-Tolerant Sequential Elements.
ATS
Mingjing Chen, Alex Orailoglu
2007 A conf
Interactive presentation: Logic level fault tolerance approaches targeting nanoelectronics PLAs.
DATE
Wenjing Rao, Alex Orailoglu, Ramesh Karri
2007 Misc conf
Light-weight synchronization for inter-processor communication acceleration on embedded MPSoCs.
CASES
Chengmo Yang, Alex Orailoglu
2007 J jnl
On the identification of modular test requirements for low cost hierarchical test path construction.
Integr.
Yiorgos Makris, Alex Orailoglu
2007 C conf
Power efficient register file update approach for embedded processors.
ICCD
Raid Ayoub, Alex Orailoglu
2007 Misc conf
Predictable execution adaptivity through embedding dynamic reconfigurability into static MPSoC schedules.
CODES+ISSS
Chengmo Yang, Alex Orailoglu
2007 J jnl
Towards Nanoelectronics Processor Architectures.
J. Electron. Test.
Wenjing Rao, Alex Orailoglu, Ramesh Karri
2006 Misc conf
Decision Tree Based Mismatch Diagnosis in Analog Circuits.
VTS
Mingjing Chen, Hosam Haggag, Alex Orailoglu
2006 B conf
Fault Identification in Reconfigurable Carry Lookahead Adders Targeting Nanoelectronic Fabrics.
ETS
Wenjing Rao, Alex Orailoglu, Ramesh Karri
2006 Misc conf
Nanofabric Topologies and Reconfiguration Algorithms to Support Dynamically Adaptive Fault Tolerance.
VTS
Wenjing Rao, Alex Orailoglu, Ramesh Karri
2006 Misc conf
Power efficient branch prediction through early identification of branch addresses.
CASES
Chengmo Yang, Alex Orailoglu
2006 C conf
Power-Constrained SOC Test Schedules through Utilization of Functional Buses.
ICCD
Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara
2006 B conf
Power-efficient instruction delivery through trace reuse.
PACT
Chengmo Yang, Alex Orailoglu
2006 A* conf
Topology aware mapping of logic functions onto nanowire-based crossbar architectures.
DAC
Wenjing Rao, Alex Orailoglu, Ramesh Karri
2005 A* conf
A DFT approach for diagnosis and process variation-aware structural test of thermometer coded current steering DACs.
DAC
Rasit Onur Topaloglu, Alex Orailoglu
2005 J jnl
A reprogrammable customization framework for efficient branch resolution in embedded processors.
ACM Trans. Embed. Comput. Syst.
Peter Petrov, Alex Orailoglu
2005 — conf
A unified transformational approach for reductions in fault vulnerability, power, and crosstalk noise & delay on processor buses.
ASP-DAC
Raid Ayoub, Alex Orailoglu
2005 C conf
Architectural-Level Fault Tolerant Computation in Nanoelectronic Processors.
ICCD
Wenjing Rao, Alex Orailoglu, Ramesh Karri
2005 J jnl
Efficient RT-Level Fault Diagnosis.
J. Comput. Sci. Technol.
Ozgur Sinanoglu, Alex Orailoglu
2005 A* conf
Energy-effcient physically tagged caches for embedded processors with virtual memory.
DAC
Peter Petrov, Daniel Tracy, Alex Orailoglu
2005 — conf
Fault tolerant nanoelectronic processor architectures.
ASP-DAC
Wenjing Rao, Alex Orailoglu, Ramesh Karri
2005 — conf
Fault tolerant quantum cellular array (QCA) design using Triple Modular Redundancy with shifted operands.
ASP-DAC
Tongquan Wei, Kaijie Wu, Ramesh Karri, Alex Orailoglu
2005 — conf
Forward discrete probability propagation method for device performance characterization under process variations.
ASP-DAC
Rasit Onur Topaloglu, Alex Orailoglu
2005 — ed.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2005, Florianolpolis, Brazil, September 4-7, 2005
SBCCI
Carlos Galup-Montoro, Sergio Bampi, Alex Orailoglu
2005 J jnl
Test power reductions through computationally efficient, decoupled scan chain modifications.
IEEE Trans. Reliab.
Ozgur Sinanoglu, Alex Orailoglu
2005 J jnl
The Construction of Optimal Deterministic Partitionings in Scan-Based BIST Fault Diagnosis: Mathematical Foundations and Cost-Effective Implementations.
IEEE Trans. Computers
Ismet Bayraktaroglu, Alex Orailoglu
2004 — conf
Application specific instruction memory transformations for power efficient, fault resilient embedded processors.
SoCC
Raid Ayoub, Peter Petrov, Alex Orailoglu
2004 A conf
Autonomous Yet Deterministic Test of SOC Cores.
ITC
Ozgur Sinanoglu, Alex Orailoglu
2004 A conf
CircularScan: A Scan Architecture for Test Cost Reduction.
DATE
Baris Arslan, Alex Orailoglu
2004 J jnl
Design of concurrent test Hardware for Linear analog circuits with constrained hardware overhead.
IEEE Trans. Very Large Scale Integr. Syst.
Sule Ozev, Alex Orailoglu
2004 A conf
Design space exploration for aggressive test cost reduction in CircularScan architectures.
ICCAD
Baris Arslan, Alex Orailoglu
2004 — conf
Efficient RT-level fault diagnosis methodology.
ASP-DAC
Ozgur Sinanoglu, Alex Orailoglu
2004 C conf
End-to-End Testability Analysis and DfT Insertion for Mixed-Signal Paths.
ICCD
Sule Ozev, Alex Orailoglu
2004 J jnl
Enhancing reliability of RTL controller-datapath circuits via Invariant-based concurrent test.
IEEE Trans. Reliab.
Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu
2004 C conf
Extending the Applicability of Parallel-Serial Scan Designs.
ICCD
Baris Arslan, Ozgur Sinanoglu, Alex Orailoglu
2004 J jnl
Fast and energy-frugal deterministic test through efficient compression and compaction techniques.
J. Syst. Archit.
Ozgur Sinanoglu, Alex Orailoglu
2004 A conf
Fault Tolerant Arithmetic with Applications in Nanotechnology based Systems.
ITC
Wenjing Rao, Alex Orailoglu, Ramesh Karri
2004 A conf
Frugal linear network-based test decompression for drastic test cost reductions.
ICCAD
Wenjing Rao, Alex Orailoglu, George Su
2004 J jnl
Low-power instruction bus encoding for embedded processors.
IEEE Trans. Very Large Scale Integr. Syst.
Peter Petrov, Alex Orailoglu
2004 — conf
On mismatch in the deep sub-micron era - from physics to circuits.
ASP-DAC
Rasit Onur Topaloglu, Alex Orailoglu
2004 B conf
Pipelined test of SOC cores through test data transformations.
ETS
Ozgur Sinanoglu, Alex Orailoglu
2004 Misc ed.
Proceedings of the 2nd IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2004, Stockholm, Sweden, September 8-10, 2004
CODES+ISSS
Alex Orailoglu, Pai H. Chou, Petru Eles, Axel Jantsch
2004 A conf
Scan Power Minimization through Stimulus and Response Transformations.
DATE
Ozgur Sinanoglu, Alex Orailoglu
2004 J jnl
Seamless Test of Digital Components in Mixed-Signal Paths.
IEEE Des. Test Comput.
Sule Ozev, Ismet Bayraktaroglu, Alex Orailoglu
2004 J jnl
Searching for Global Test Costs Optimization in Core-Based Systems.
J. Electron. Test.
Érika F. Cota, Luigi Carro, Marcelo Lubaszewski, Alex Orailoglu
2004 J jnl
Tag compression for low power in dynamically customizable embedded processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Peter Petrov, Alex Orailoglu
2004 A conf
Test Cost Reduction Through A Reconfigurable Scan Architecture.
ITC
Baris Arslan, Alex Orailoglu
2004 J jnl
Transforming Binary Code for Low-Power Embedded Processors.
IEEE Micro
Peter Petrov, Alex Orailoglu
2003 C conf
Aggressive Test Power Reduction Through Test Stimuli Transformation.
ICCD
Ozgur Sinanoglu, Alex Orailoglu
2003 J jnl
Application-Specific Instruction Memory Customizations for Power-Efficient Embedded Processors.
IEEE Des. Test Comput.
Peter Petrov, Alex Orailoglu
2003 J jnl
Compacting Test Responses for Deeply Embedded SoC Cores.
IEEE Des. Test Comput.
Ozgur Sinanoglu, Alex Orailoglu
2003 A conf
Compiler-Based Register Name Adjustment for Low-Power Embedded Processors.
ICCAD
Peter Petrov, Alex Orailoglu
2003 J jnl
Concurrent Application of Compaction and Compression for Test Time and Data Volume Reduction in Scan Designs.
IEEE Trans. Computers
Ismet Bayraktaroglu, Alex Orailoglu
2003 C conf
Customizable Embedded Processor Architectures.
DSD
Peter Petrov, Alex Orailoglu
2003 Misc conf
Decompression Hardware Determination for Test Volume and Time Reduction through Unified Test Pattern Compaction and Compression.
VTS
Ismet Bayraktaroglu, Alex Orailoglu
2003 — conf
Extracting Precise Diagnosis of Bridging Faults from Stuck-at Fault Information.
Asian Test Symposium
Baris Arslan, Alex Orailoglu
2003 J jnl
Guest Editor's Introduction.
Int. J. Parallel Program.
Alex Orailoglu
2003 J jnl
Guest Editors' Introduction: Application-Specific Microprocessors.
IEEE Des. Test Comput.
Alex Orailoglu, Alexander V. Veidenbaum
2003 C conf
Hierarchical Constraint Conscious RT-level Test Generation.
DSD
Ozgur Sinanoglu, Alex Orailoglu
2003 C conf
Low-power Branch Target Buffer for Application-Specific Embedded Processors.
DSD
Peter Petrov, Alex Orailoglu
2003 A conf
Modeling Scan Chain Modifications For Scan-in Test Power Minimization.
ITC
Ozgur Sinanoglu, Alex Orailoglu
2003 — conf
Parity-based output compaction for core-based SOCs [logic testing].
ETW
Ozgur Sinanoglu, Alex Orailoglu
2003 A conf
Partial Core Encryption for Performance-Efficient Test of SOCs.
ICCAD
Ozgur Sinanoglu, Alex Orailoglu
2003 A conf
Power Efficiency through Application-Specific Instruction Memory Transformations.
DATE
Peter Petrov, Alex Orailoglu
2003 Misc ed.
Proceedings of the 1st IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2003, Newport Beach, CA, USA, October 1-3, 2003
CODES+ISSS
Rajesh Gupta, Yukihiro Nakamura, Alex Orailoglu, Pai H. Chou
2003 J jnl
Reducing Average and Peak Test Power Through Scan Chain Modification.
J. Electron. Test.
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu
2003 J jnl
Statistical Tolerance Analysis for Assured Analog Test Coverage.
J. Electron. Test.
Sule Ozev, Alex Orailoglu
2003 — conf
Test Data Manipulation Techniques for Energy-Frugal, Rapid Scan Test.
Asian Test Symposium
Ozgur Sinanoglu, Alex Orailoglu
2003 A* conf
Test application time and volume compression through seed overlapping.
DAC
Wenjing Rao, Ismet Bayraktaroglu, Alex Orailoglu
2003 A conf
Virtual Compression through Test Vector Stitching for Scan Based Designs.
DATE
Wenjing Rao, Alex Orailoglu
2003 C conf
Virtual Page Tag Reduction for Low-power TLBs.
ICCD
Peter Petrov, Alex Orailoglu
2002 A conf
A novel scan architecture for power-efficient, rapid test.
ICCAD
Ozgur Sinanoglu, Alex Orailoglu
2002 — conf
An Integrated Tool for Analog Test Generation and Fault Simulation.
ISQED
Sule Ozev, Alex Orailoglu
2002 — conf
Automated test development and test time reduction for RF subsystems.
ISCAS (1)
Sule Ozev, Alex Orailoglu, Hosam Haggag
2002 Misc conf
Boosting the Accuracy of Analog Test Coverage Computation through Statistical Tolerance Analysis.
VTS
Sule Ozev, Alex Orailoglu
2002 C conf
Cost-Effective Concurrent Test Hardware Design for Linear Analog Circuits.
ICCD
Sule Ozev, Alex Orailoglu
2002 J jnl
Cost-Effective Deterministic Partitioning for Rapid Diagnosis in Scan-Based BIST.
IEEE Des. Test Comput.
Ismet Bayraktaroglu, Alex Orailoglu
2002 — conf
Dynamic test data transformations for average and peak power reductions.
ETW
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu
2002 J jnl
Efficient Construction of Aliasing-Free Compaction Circuitry.
IEEE Micro
Ozgur Sinanoglu, Alex Orailoglu
2002 — conf
Energy frugal tags in reprogrammable I-caches for application-specific embedded processors.
CODES
Peter Petrov, Alex Orailoglu
2002 J jnl
Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface.
J. Electron. Test.
Yiorgos Makris, Jamison Collins, Alex Orailoglu
2002 — conf
Fast and Energy-Frugal Deterministic Test Through Test Vector Correlation Exploitation.
DFT
Ozgur Sinanoglu, Alex Orailoglu
2002 C conf
Fault Dictionary Size Reduction through Test Response Superposition.
ICCD
Baris Arslan, Alex Orailoglu
2002 A conf
Gate Level Fault Diagnosis in Scan-Based BIST.
DATE
Ismet Bayraktaroglu, Alex Orailoglu
2002 — conf
Generic and Detailed Search for TAM Definition in Core-Based Systems.
LATW
Érika F. Cota, Luigi Carro, Alex Orailoglu, Marcelo Lubaszewski
2002 — conf
Low-Power Data Memory Communication for Application-Specific Embedded Processors.
ISSS
Alex Orailoglu, Peter Petrov
2002 J jnl
Microarchitectural synthesis of performance-constrained, low-power VLSI designs.
ACM Trans. Design Autom. Electr. Syst.
Laurence Goodby, Alex Orailoglu, Paul M. Chau
2002 J jnl
Multilevel Testability Analysis and Solutions for Integrated Bluetooth Transceivers.
IEEE Des. Test Comput.
Sule Ozev, Christian Olgaard, Alex Orailoglu
2002 — conf
On the Relation between SAT and BDDs for Equivalence Checking.
ISQED
Sherief Reda, Rolf Drechsler, Alex Orailoglu
2002 A conf
Power Efficient Embedded Processor Ip's through Application-Specific Tag Compression in Data Caches.
DATE
Peter Petrov, Alex Orailoglu
2002 A conf
Reducing Test Application Time Through Test Data Mutation Encoding.
DATE
Sherief Reda, Alex Orailoglu
2002 A conf
Scan Power Reduction Through Test Data Transition Frequency Analysis.
ITC
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu
2002 A conf
Test Planning and Design Space Exploration in a Core-Based Environment.
DATE
Érika F. Cota, Luigi Carro, Marcelo Lubaszewski, Alex Orailoglu
2002 Misc conf
Test Power Reduction through Minimization of Scan Chain Transitions.
VTS
Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu
2002 — conf
Test Requirement Analysis for Low Cost Hierarchical Test Path Construction.
Asian Test Symposium
Yiorgos Makris, Alex Orailoglu
2001 — conf
Compaction Schemes with Minimum Test Application Time.
Asian Test Symposium
Ozgur Sinanoglu, Alex Orailoglu
2001 J jnl
Concurrent test for digital linear systems.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ismet Bayraktaroglu, Alex Orailoglu
2001 — conf
Data cache energy minimizations through programmable tag size matching to the applications.
ISSS
Peter Petrov, Alex Orailoglu
2001 A conf
Diagnosis for scan-based BIST: reaching deep into the signatures.
DATE
Ismet Bayraktaroglu, Alex Orailoglu
2001 Misc conf
Efficient Transparency Extraction and Utilization in Hierarchical Test.
VTS
Yiorgos Makris, Vishal Patel, Alex Orailoglu
2001 — conf
Faults in Processor Control Subsystems: Testing Correctness and Performance Faults in the Data Prefetching Unit.
Asian Test Symposium
Sobeeh Almukhaizim, Peter Petrov, Alex Orailoglu
2001 — conf
Improved Methods for Fault Diagnosis in Scan-Based BIST.
LATW
Ismet Bayraktaroglu, Alex Orailoglu
2001 — conf
Low-cost, software-based self-test methodologies for performance faults in processor control subsystems.
CICC
Sobeeh Almukhaizim, Peter Petrov, Alex Orailoglu
2001 J jnl
Performance and power effectiveness in embedded processors customizable partitioned caches.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Peter Petrov, Alex Orailoglu
2001 Misc conf
RT-level Fault Simulation Based on Symbolic Propagation.
VTS
Ozgur Sinanoglu, Alex Orailoglu
2001 — conf
Selecting a PRPG: Randomness, Primitiveness, or Sheer Luck?
Asian Test Symposium
Ismet Bayraktaroglu, Alex Orailoglu
2001 A conf
Space and time compaction schemes for embedded cores.
ITC
Ozgur Sinanoglu, Alex Orailoglu
2001 A* conf
Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors.
DAC
Peter Petrov, Alex Orailoglu
2001 A* conf
Test Volume and Application Time Reduction Through Scan Chain Concealment.
DAC
Ismet Bayraktaroglu, Alex Orailoglu
2001 A conf
Testability implications in low-cost integrated radio transceivers: a Bluetooth case study.
ITC
Christian Olgaard, Sule Ozev, Alex Orailoglu
2001 — conf
Towards effective embedded processors in codesigns: customizable partitioned caches.
CODES
Peter Petrov, Alex Orailoglu
2000 — conf
Accumulation-based concurrent fault detection for linear digital state variable systems.
Asian Test Symposium
Ismet Bayraktaroglu, Alex Orailoglu
2000 — conf
Block-Based Test Integration for Analog Integrated Circuits.
LATW
Sule Ozev, Alex Orailoglu
2000 Misc conf
Cost effective digital filter design for concurrent test.
ICASSP
Ismet Bayraktaroglu, Alex Orailoglu
2000 A conf
Deterministic partitioning techniques for fault diagnosis in scan-based BIST.
ITC
Ismet Bayraktaroglu, Alex Orailoglu
2000 — conf
Exploiting Off-Line Hierarchical Test Paths in Module Diagnosis and On-Line Test.
LATW
Yiorgos Makris, Alex Orailoglu
2000 — conf
Fast hierarchical test path construction for DFT-free controller-datapath circuits.
Asian Test Symposium
Yiorgos Makris, Jamison Collins, Alex Orailoglu
2000 — conf
How to avoid random walks in hierarchical test path identification.
ETW
Yiorgos Makris, Jamison Collins, Alex Orailoglu
2000 A* conf
Improved fault diagnosis in scan-based BIST via superposition.
DAC
Ismet Bayraktaroglu, Alex Orailoglu
2000 Misc conf
Invariance-Based On-Line Test for RTL Controller-Datapath Circuits.
VTS
Yiorgos Makris, Ismet Bayraktaroglu, Alex Orailoglu
2000 — conf
Low cost concurrent test implementation for linear digital systems.
ETW
Ismet Bayraktaroglu, Alex Orailoglu
2000 — conf
Modular test generation and concurrent transparency-based test translation using gate-level ATPG.
CICC
Yiorgos Makris, Alex Orailoglu, Praveen Vishakantaiah
2000 J jnl
On-line test for fault-secure fault identification.
IEEE Trans. Very Large Scale Integr. Syst.
Samuel Norman Hamilton, Alex Orailoglu
2000 A conf
Test Quality and Fault Risk in Digital Filter Datapath BIST.
DATE
Laurence Goodby, Alex Orailoglu
2000 Misc conf
Test Selection Based on High Level Fault Simulation for Mixed-Signal Systems.
VTS
Sule Ozev, Alex Orailoglu
2000 A conf
Test Synthesis for Mixed-Signal SOC Paths.
DATE
Sule Ozev, Ismet Bayraktaroglu, Alex Orailoglu
2000 C conf
Transparency-based hierarchical test generation for modular RTL designs.
ISCAS
Yiorgos Makris, Jamison Collins, Alex Orailoglu, Praveen Vishakantaiah
2000 C conf
Unifying methodologies for high fault coverage concurrent and off-line test of digital filters.
ISCAS
Ismet Bayraktaroglu, Alex Orailoglu
1999 — conf
A Module Diagnosis and Design-for-Debug Methodology Based on Hierarchical Test Paths.
DFT
Yiorgos Makris, Alex Orailoglu
1999 A conf
Channel-Based Behavioral Test Synthesis for Improved Module Reachability.
DATE
Yiorgos Makris, Alex Orailoglu
1999 Misc conf
Low-Cost On-Line Test for Digital Filters.
VTS
Ismet Bayraktaroglu, Alex Orailoglu
1999 — conf
Low-Cost Test for Large Analog IC's.
DFT
Sule Ozev, Alex Orailoglu
1999 — conf
Property-based testability analysis for hierarchical RTL designs.
ICECS
Yiorgos Makris, Alex Orailoglu
1999 J jnl
Redundancy and testability in digital filter datapaths.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Laurence Goodby, Alex Orailoglu
1999 A conf
Self Recovering Controller and Datapath Codesign.
DATE
Samuel Norman Hamilton, Alex Orailoglu, Andre Hertwig
1999 — conf
TRANSPARENT: a system for RTL testability analysis, DFT guidance and hierarchical test generation.
CICC
Yiorgos Makris, Jamison Collins, Alex Orailoglu, Praveen Vishakantaiah
1998 — conf
An Examination of PRPG Selection Approaches for Large, Industrial Designs.
Asian Test Symposium
Ismet Bayraktaroglu, K. Udawatta, Alex Orailoglu
1998 A conf
Concurrent Error Recovery with Near-Zero Latency in Synthesized ASICs.
DATE
Samuel Norman Hamilton, Alex Orailoglu
1998 A conf
DFT guidance through RTL test justification and propagation analysis.
ITC
Yiorgos Makris, Alex Orailoglu
1998 J jnl
Efficient Self-Recovering ASIC Design.
IEEE Des. Test Comput.
Samuel Norman Hamilton, Alex Orailoglu
1998 — conf
Graceful Degradation in Synthesis of VLSI ICs.
DFT
Alex Orailoglu
1998 J jnl
On-Line Fault Resilience Through Gracefully Degradable ASICs.
J. Electron. Test.
Alex Orailoglu
1998 J jnl
RTL Test Justification and Propagation Analysis for Modular Designs.
J. Electron. Test.
Yiorgos Makris, Alex Orailoglu
1998 — conf
Transient and Intermittent Fault Recovery without Rollback.
DFT
Samuel Norman Hamilton, Alex Orailoglu
1997 A* conf
Frequency-Domain Compatibility in Digital Filter BIST.
DAC
Laurence Goodby, Alex Orailoglu
1997 — conf
Microarchitectural Synthesis of ICs with Embedded Concurrent Fault Isolation.
FTCS
Samuel Norman Hamilton, Alex Orailoglu
1997 J jnl
Microarchitectural synthesis for rapid BIST testing.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Alex Orailoglu
1997 J jnl
Module Selection in Microarchitectural Synthesis for Multiple Critical Constraint Satisfaction.
VLSI Design
Ian G. Harris, Alex Orailoglu
1996 J jnl
Automatic Synthesis of Self-Recovering VLSI Systems.
IEEE Trans. Computers
Alex Orailoglu, Ramesh Karri
1996 Misc conf
Can Defect-Tolerant Chips Better Meet the Quality Challenge?
VTS
R. L. Campbell, P. Kuekes, David Y. Lepejian, Wojciech P. Maly, Michael Nicolaidis, Alex Orailoglu
1996 J jnl
Computer-Aided Design of Fault-Tolerant VLSI Systems.
IEEE Des. Test Comput.
Ramesh Karri, Karin Högstedt, Alex Orailoglu
1996 — conf
High-level synthesis of gracefully degradable ASICs.
ED&TC
Wah Chan, Alex Orailoglu
1996 C conf
Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs.
ICCD
Alex Orailoglu
1996 A* conf
Pseudorandom-Pattern Test Resistance in High-Performance DSP Datapaths.
DAC
Laurence Goodby, Alex Orailoglu
1996 J jnl
Time-constrained scheduling during high-level synthesis of fault-secure VLSI digital signal processors.
IEEE Trans. Reliab.
Ramesh Karri, Alex Orailoglu
1996 Misc conf
Variance mismatch: identifying random-test resistance in DSP datapaths.
ICASSP
Laurence Goodby, Alex Orailoglu
1995 — conf
Metric-based transformations for self testable VLSI designs with high test concurrency.
EURO-DAC
Mahsa Vahidi, Alex Orailoglu
1995 Misc conf
Testability metrics for synthesis of self-testable designs and effective test plans.
VTS
Mahsa Vahidi, Alex Orailoglu
1995 A conf
Towards 100% Testable FIR Digital Filters.
ITC
Laurence Goodby, Alex Orailoglu
1994 A* conf
Area-Efficient Fault Detection During Self-Recovering Microarchitecture Synthesis.
DAC
Ramesh Karri, Alex Orailoglu
1994 J jnl
Coactive scheduling and checkpoint determination during high level synthesis of self-recovering microarchitectures.
IEEE Trans. Very Large Scale Integr. Syst.
Alex Orailoglu, Ramesh Karri
1994 — conf
Fine-Grained Concurrency in Test Scheduling for Partial-Intrusion BIST.
EDAC-ETC-EUROASIC
Ian G. Harris, Alex Orailoglu
1994 C conf
Integrating Binding Constraints in the Synthesis of Area-Efficient Self-Recovering Microarchitectures.
ICCD
Karin Högstedt, Alex Orailoglu
1994 C conf
Microarchitectural Synthesis of Performance-Constrained, Low-Power VLSI Designs.
ICCD
Laurence Goodby, Alex Orailoglu, Paul M. Chau
1994 A* conf
Microarchitectural Synthesis of VLSI Designs with High Test Concurrency.
DAC
Ian G. Harris, Alex Orailoglu
1994 — conf
Rapid prototyping of fault-tolerant VLSI systems.
HLSS
Ramesh Karri, Karin Högstedt, Alex Orailoglu
1994 C conf
SYNCBIST: SYNthesis for Concurrent Built-In-Self-Testability.
ICCD
Ian G. Harris, Alex Orailoglu
1994 — conf
Simulated annealing based yield enhancement of layouts.
Great Lakes Symposium on VLSI
Ramesh Karri, Alex Orailoglu
1994 J jnl
Synthesis of fault-tolerant and real-time microarchitectures.
J. Syst. Softw.
Alex Orailoglu, Ramesh Karri
1993 A* conf
High-Level Synthesis of Fault-Secure Microarchitectures.
DAC
Ramesh Karri, Alex Orailoglu
1993 C conf
Intertwined Scheduling, Module Selection and Allocation in Time-and-Area.
ISCAS
Ian G. Harris, Alex Orailoglu
1993 — conf
Optimal Self-Recovering Microarchitecture Synthesis.
FTCS
Ramesh Karri, Alex Orailoglu
1993 C conf
Test Path Generation and Test Scheduling for Self-Testable Designs.
ICCD
Alex Orailoglu, Ian G. Harris
1992 C conf
High-Level Synthesis of Self-Recovering MicroArchitectures.
ICCD
Alex Orailoglu, Ramesh Karri
1992 — conf
Scheduling with Rollback Constraints in High-Level Synthesis of Self-Recovering ASICs.
FTCS
Ramesh Karri, Alex Orailoglu
1992 A* conf
Transformation-Based High-Level Synthesis of Fault-Tolerant ASICs.
DAC
Ramesh Karri, Alex Orailoglu
1991 A* conf
ALPS: An Algorithm for Pipeline Data Path Synthesis.
MICRO
Ramesh Karri, Alex Orailoglu
1991 J jnl
Hierarchical Modeling of the VLSI Design Process.
IEEE Expert
Amir K. Hekmatpour, Alex Orailoglu, Paul M. Chau
1986 A* conf
Flow graph representation.
DAC
Alex Orailoglu, Daniel Gajski
1983 — —
Software Design Issues in the Implementation of Hierarchical, Display Editors
Alex Orailoglu