Alessio Spessot

24 papers A* 1A 1Journal 1Unranked 21

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	Gate Stack Development for Next Gen High Voltage Periphery DRAM Devices. IRPS J. P. Bastos, Jacopo Franco, Barry J. O'Sullivan, Yusuke Higashi, Adrian Chasin, J. Ganguly, Hiroaki Arimura, Alessio Spessot, M.-S. Kim, N. Horiguchi
2024	—	`conf`	DRAM-Peri FinFET - A Thermally-Stable High-Performance Advanced CMOS RMG Platform with Mo-Based pWFM for sub-10nm DRAM. VLSI Technology and Circuits J. Ganguly, Hiroaki Arimura, Romain Ritzenthaler, H. Bana, J. W. Maes, J. G. Lai, S. Brus, W. Maqsood, R. Sarkar, B. Kannan, Elena Capogreco, V. Machkaoutsan, S. Yoon, Alessio Spessot, M. Givens, Naoto Horiguchi
2024	—	`conf`	Side and Corner Region Non-Uniformities in Grown SiO2 and Their Implications on Current, Capacitance and Breakdown Characteristics. IRPS J. P. Bastos, Barry J. O'Sullivan, Yusuke Higashi, Adrian Vaisman Chasin, Jacopo Franco, Hiroaki Arimura, J. Ganguly, Elena Capogreco, Alessio Spessot, N. Horiguchi
2022	—	`conf`	Bias Temperature Instability (BTI) of High-Voltage Devices for Memory Periphery. IRPS J. P. Bastos, Barry J. O'Sullivan, Jacopo Franco, Stanislav Tyaginov, Brecht Truijen, Adrian Vaisman Chasin, Robin Degraeve, Ben Kaczer, Romain Ritzenthaler, Elena Capogreco, E. Dentoni Litta, Alessio Spessot, Yusuke Higashi, Y. Yoon, V. Machkaoutsan, Pierre Fazan, N. Horiguchi
2022	—	`conf`	High Performance Thermally Resistant FinFETs DRAM Peripheral CMOS FinFETs with VTH Tunability for Future Memories. VLSI Technology and Circuits Romain Ritzenthaler, Elena Capogreco, E. Dupuy, Hiroaki Arimura, J. P. Bastos, P. Favia, F. Sebaai, D. Radisic, V. T. H. Nguyen, G. Mannaert, B. T. Chan, V. Machkaoutsan, Y. Yoon, H. Itokawa, M. Yamaguchi, Y. Chen, Pierre Fazan, S. Subramanian, Alessio Spessot, E. Dentoni Litta, S. Samavedam, Naoto Horiguchi
2022	J	`jnl`	Multitimescale Mitigation for Performance Variability Improvement in Time-Critical Systems. IEEE Trans. Very Large Scale Integr. Syst. Ji-Yung Lin, Pieter Weckx, Subrat Mishra, Alessio Spessot, Francky Catthoor
2022	A	`conf`	Proactive Run-Time Mitigation for Time-Critical Applications Using Dynamic Scenario Methodology. DATE Ji-Yung Lin, Pieter Weckx, Subrat Mishra, Alessio Spessot, Francky Catthoor
2022	—	`conf`	Thermally stable, packaged aware LV HKMG platforms benchmark to enable low power I/O for next 3D NAND generations. IMW Alessio Spessot, Shairfe Muhammad Salahuddin, Ricardo Escobar, Romain Ritzenthaler, Yang Xiang, Rahul Budhwani, Eugenio Dentoni Litta, Elena Capogreco, Joao P. Bastos, Yangyin Chen, Naoto Horiguchi
2021	—	`conf`	Overhead Reduction with Optimal Margining Using A Reliability Aware Design Paradigm. IRPS Subrat Mishra, Pieter Weckx, Odysseas Zografos, Ji-Yung Lin, Alessio Spessot, Francky Catthoor
2020	—	`conf`	Device Scaling roadmap and its implications for Logic and Analog platform. BCICTS Alessio Spessot, Bertrand Parvais, Amita Rawat, Kenichi Miyaguchi, Pieter Weckx, Doyoung Jang, Julien Ryckaert
2020	—	`conf`	Fast & Accurate Methodology for Aging Incorporation in Circuits using Adaptive Waveform Splitting (AWS). IRPS Subrat Mishra, Pieter Weckx, Ji-Yung Lin, Ben Kaczer, Dimitri Linten, Alessio Spessot, Francky Catthoor
2020	—	`conf`	Relevance of fin dimensions and high-pressure anneals on hot-carrier degradation. IRPS Adrian Vaisman Chasin, Jacopo Franco, Erik Bury, Romain Ritzenthaler, Eugenio Dentoni Litta, Alessio Spessot, Naoto Horiguchi, Dimitri Linten, Ben Kaczer
2019	—	`conf`	Gate-Stack Engineered NBTI Improvements in Highvoltage Logic-For-Memory High-ĸ/Metal Gate Devices. IRPS Barry J. O'Sullivan, Romain Ritzenthaler, Gerhard Rzepa, Z. Wu, E. Dentoni Litta, O. Richard, T. Conard, V. Machkaoutsan, Pierre Fazan, C. Kim, Jacopo Franco, Ben Kaczer, Tibor Grasser, Alessio Spessot, Dimitri Linten, N. Horiguchi
2019	A*	`conf`	Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM Applications. DAC Trong Huynh Bao, Anabela Veloso, Sushil Sakhare, Philippe Matagne, Julien Ryckaert, Manu Perumkunnil, Davide Crotti, Farrukh Yasin, Alessio Spessot, Arnaud Furnémont, Gouri Sankar Kar, Anda Mocuta
2017	—	`conf`	Dedicated technology threshold voltage tuning for 6T SRAM beyond N7. ICICDT Mohit Kumar Gupta, Pieter Weckx, Stefan Cosemans, Pieter Schuddinck, Rogier Baert, Doyoung Jang, Yasser Sherazi, Praveen Raghavan, Alessio Spessot, Anda Mocuta, Wim Dehaene
2017	—	`conf`	Device circuit and technology co-optimisation for FinFET based 6T SRAM cells beyond N7. ESSDERC Mohit Kumar Gupta, Pieter Weckx, Stefan Cosemans, Pieter Schuddinck, Rogier Baert, Dmitry Yakimets, Doyoung Jang, Yasser Sherazi, Praveen Raghavan, Alessio Spessot, Anda Mocuta, Wim Dehaene
2017	—	`conf`	SRAM designs for 5nm node and beyond: Opportunities and challenges. ICICDT Trong Huynh Bao, Sushil Sakhare, Julien Ryckaert, Alessio Spessot, Diederik Verkest, Anda Mocuta
2015	—	`conf`	Assessment of SiGe quantum well transistors for DRAM peripheral applications. ICICDT Romain Ritzenthaler, Tom Schram, Geert Eneman, Anda Mocuta, Naoto Horiguchi, Aaron Voon-Yew Thean, Alessio Spessot, Marc Aoulaiche, Pierre Fazan, K. B. Noh, Y. Son
2015	—	`conf`	I/O thick oxide device integration using Diffusion and Gate Replacement (D&GR) gate stack integration. ICICDT Romain Ritzenthaler, Tom Schram, M. J. Cho, Anda Mocuta, Naoto Horiguchi, Aaron Voon-Yew Thean, Alessio Spessot, Christian Caillat, Marc Aoulaiche, Pierre Fazan, K. B. Noh, Y. Son
2015	—	`conf`	Off-state stress degradation mechanism on advanced p-MOSFETs. ICICDT Moonju Cho, Alessio Spessot, Ben Kaczer, Marc Aoulaiche, Romain Ritzenthaler, Tom Schram, Pierre Fazan, Naoto Horiguchi, Dimitri Linten
2015	—	`conf`	Reliability impact of advanced doping techniques for DRAM peripheral MOSFETs. ICICDT Alessio Spessot, Romain Ritzenthaler, Tom Schram, Marc Aoulaiche, Moonju Cho, Maria Toledano-Luque, Naoto Horiguchi, Pierre Fazan
2014	—	`conf`	Impact of Off State Stress on advanced high-K metal gate NMOSFETs. ESSDERC Alessio Spessot, Marc Aoulaiche, Moonju Cho, Jacopo Franco, Tom Schram, Romain Ritzenthaler, Ben Kaczer
2013	—	`conf`	Impact of Al2O3 position on performances and reliability in high-k metal gated DRAM periphery transistors. ESSDERC Marc Aoulaiche, Eddy Simoen, Romain Ritzenthaler, Tom Schram, Hiroaki Arimura, Moonju Cho, Thomas Kauerauf, Guido Groeseneken, Naoto Horiguchi, Aaron Thean, Antonio Federico, Felice Crupi, Alessio Spessot, Christian Caillat, Pierre Fazan, Hyuokju Na, Y. Son, K. B. Noh
2012	—	`conf`	Low-power DRAM-compatible Replacement Gate High-k/Metal Gate stacks. ESSDERC Romain Ritzenthaler, Tom Schram, Erik Bury, Jérôme Mitard, L.-Å. Ragnarsson, Guido Groeseneken, N. Horiguchi, Aaron Thean, Alessio Spessot, Christian Caillat, V. Srividya, Pierre Fazan