Alessio Santiccioli

17 papers Journal 9Unranked 7
YearRankTypeTitle / Venue / Authors
2023 J jnl
A 72-fs-Total-Integrated-Jitter Two-Core Fractional-N Digital PLL With Digital Period Averaging Calibration on Frequency Quadrupler and True-in-Phase Combiner.
IEEE J. Solid State Circuits
Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2023 J jnl
A Novel LO Phase-Shifting System Based on Digital Bang-Bang PLLs With Background Phase-Offset Correction for Integrated Phased Arrays.
IEEE J. Solid State Circuits
Francesco Tesolin, Simone Mattia Dartizio, Francesco Buccoleri, Alessio Santiccioli, Luca Bertulessi, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2022 J jnl
A 12.5-GHz Fractional-N Type-I Sampling PLL Achieving 58-fs Integrated Jitter.
IEEE J. Solid State Circuits
Mario Mercandelli, Alessio Santiccioli, Angelo Parisi, Luca Bertulessi, Dmytro Cherniak, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino
2022 J jnl
A 12.9-to-15.1-GHz Digital PLL Based on a Bang-Bang Phase Detector With Adaptively Optimized Noise Shaping.
IEEE J. Solid State Circuits
Simone Mattia Dartizio, Francesco Tesolin, Mario Mercandelli, Alessio Santiccioli, Abanob Shehata, Saleh Karman, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Andrea L. Lacaita, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino
2022 — conf
A 68.6fs
ISSCC
Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea Leonardo Lacaita, Salvatore Levantino
2022 — conf
A 9GHz 72fs-Total-lntegrated-Jitter Fractional-N Digital PLL with Calibrated Frequency Quadrupler.
CICC
Francesco Buccoleri, Simone Mattia Dartizio, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Andrea Bevilacqua, Luca Bertulessi, Dmytro Cherniak, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2022 J jnl
A Fractional-N Bang-Bang PLL Based on Type-II Gear Shifting and Adaptive Frequency Switching Achieving 68.6 fs-rms-Total-Integrated-Jitter and 1.56 μs-Locking-Time.
IEEE J. Solid State Circuits
Simone Mattia Dartizio, Francesco Buccoleri, Francesco Tesolin, Luca Avallone, Alessio Santiccioli, Agata Iesurum, Giovanni Steffan, Dmytro Cherniak, Luca Bertulessi, Andrea Bevilacqua, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino
2021 — conf
32.8 A 98.4fs-Jitter 12.9-to-15.1GHz PLL-Based LO Phase-Shifting System with Digital Background Phase-Offset Correction for Integrated Phased Arrays.
ISSCC
Alessio Santiccioli, Mario Mercandelli, Simone Mattia Dartizio, Francesco Tesolin, Saleh Karman, Abanob Shehata, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Dmytro Cherniak, Andrea L. Lacaita, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino
2021 — conf
A 12.9-to-15.1GHz Digital PLL Based on a Bang-Bang Phase Detector with Adaptively Optimized Noise Shaping Achieving 107.6fs Integrated Jitter.
ISSCC
Mario Mercandelli, Alessio Santiccioli, Simone Mattia Dartizio, Abanob Shehata, Francesco Tesolin, Saleh Karman, Luca Bertulessi, Francesco Buccoleri, Luca Avallone, Angelo Parisi, Andrea Leonardo Lacaita, Michael Peter Kennedy, Carlo Samori, Salvatore Levantino
2021 J jnl
A Comprehensive Phase Noise Analysis of Bang-Bang Digital PLLs.
IEEE Trans. Circuits Syst. I Regul. Pap.
Luca Avallone, Mario Mercandelli, Alessio Santiccioli, Michael Peter Kennedy, Salvatore Levantino, Carlo Samori
2020 — conf
17.2 A 66fsrmsJitter 12.8-to-15.2GHz Fractional-N Bang-Bang PLL with Digital Frequency-Error Recovery for Fast Locking.
ISSCC
Alessio Santiccioli, Mario Mercandelli, Luca Bertulessi, Angelo Parisi, Dmytro Cherniak, Andrea Leonardo Lacaita, Carlo Samori, Salvatore Levantino
2020 — conf
17.5 A 12.5GHz Fractional-N Type-I Sampling PLL Achieving 58fs Integrated Jitter.
ISSCC
Mario Mercandelli, Alessio Santiccioli, Angelo Parisi, Luca Bertulessi, Dmytro Cherniak, Andrea Leonardo Lacaita, Carlo Samori, Salvatore Levantino
2020 J jnl
A 66-fs-rms Jitter 12.8-to-15.2-GHz Fractional-N Bang-Bang PLL With Digital Frequency-Error Recovery for Fast Locking.
IEEE J. Solid State Circuits
Alessio Santiccioli, Mario Mercandelli, Luca Bertulessi, Angelo Parisi, Dmytro Cherniak, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino
2020 — —
High-efficiency inductorless frequency synthesis.
Alessio Santiccioli
2019 J jnl
A 1.6-to-3.0-GHz Fractional-N MDLL With a Digital-to-Time Converter Range-Reduction Technique Achieving 397-fs Jitter at 2.5-mW Power.
IEEE J. Solid State Circuits
Alessio Santiccioli, Mario Mercandelli, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino
2019 — conf
A 1.6-to-3.0-GHz Fractional-N MDLL with a Digital-to-Time Converter Range-Reduction Technique Achieving 397fs Jitter at 2.5-mW Power.
CICC
Alessio Santiccioli, Mario Mercandelli, Andrea L. Lacaita, Carlo Samori, Salvatore Levantino
2019 J jnl
Time-Variant Modeling and Analysis of Multiplying Delay-Locked Loops.
IEEE Trans. Circuits Syst. I Regul. Pap.
Alessio Santiccioli, Carlo Samori, Andrea L. Lacaita, Salvatore Levantino