Alessandro Trifiletti

173 papers A 2B 1C 27Journal 69Unranked 74
YearRankTypeTitle / Venue / Authors
2025 C conf
A Novel Ultra-Low-Power, Tunable, LPF and BPF Biquad Based on New Fully Differential Folded-Gain-Boosting.
ISCAS
Matteo Lombardo, Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2025 J jnl
Exploiting Body-Driven Feedbacks in Physical Unclonable Functions for Ultra Low Voltage, Ultra Low Power Applications: A 0.3 V Weak-PUF.
IEEE Trans. Circuits Syst. I Regul. Pap.
Riccardo Della Sala, Davide Bellizia, Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti
2025 — conf
Fast FPGA-Based Implementation of the QP-Dyn Stream Cipher using High-Level Synthesis.
HPEC
Paolo Palazzari, Luigi Accardi, Antonio Mastrandrea, Pasquale Tommasino, Alessandro Trifiletti
2025 J jnl
Low-Gm tunable CMOS transconductors for simultaneous multi-sine bioimpedance spectroscopy.
Integr.
Israel Corbacho, Pietro Monsurrò, Francisco Romero-Galán, Miguel Angel Domínguez, Alessandro Trifiletti, Juan M. Carrillo
2024 — conf
A 150 MS/s, 10 bit SAR ADC Featuring a Modified Quasi-Monotonic Switching Scheme.
PRIME
Valerio Spinogatti, Cristian Bocciarelli, Lorenzo Eusebio, Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti
2024 J jnl
An Intermodulation Radar for Non-Linear Target and Transceiver Detection.
Sensors
Stefano Pisa, Alessandro Trifiletti, Pasquale Tommasino, Pietro Monsurrò, Piero Tognolatti, Giorgio Leuzzi, Alessandro Di Carlofelice, Emidio Di Giampaolo
2024 — conf
Enhancing Performance of Ultra-Low Voltage Body-Driven Comparators Through Clocked Supply Voltage.
PRIME
Riccardo Della Sala, Cristian Bocciarelli, Valerio Spinogatti, Francesco Centurelli, Alessandro Trifiletti
2023 J jnl
A 0.3V Rail-to-Rail Three-Stage OTA With High DC Gain and Improved Robustness to PVT Variations.
IEEE Access
Riccardo Della Sala, Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
2023 J jnl
A 17 GHz inductorless low-pass filter based on a quasi-Sallen-Key approach.
Int. J. Circuit Theory Appl.
Cristian Bocciarelli, Francesco Centurelli, Pietro Monsurrò, Valerio Spinogatti, Alessandro Trifiletti
2023 — conf
A 2.5 GHz, 0.6 V Body Driven Dynamic Comparator Exploiting Charge Pump Based Dynamic Biasing.
PRIME
Cristian Bocciarelli, Francesco Centurelli, Riccardo Della Sala, Valerio Spinogatti, Alessandro Trifiletti
2023 J jnl
A Novel Parallel Digitizer With a Pulseless Mixing-Filtering-Processing Architecture and Its Implementation in a SiGe HBT Technology at 40GS/s.
IEEE Access
Francesco Centurelli, Pietro Monsurrò, Pasquale Tommasino, Alessandro Trifiletti
2023 — conf
A Novel Ultra-Low Voltage Fully Synthesizable Comparator exploiting NAND Gates.
PRIME
Riccardo Della Sala, Cristian Bocciarelli, Francesco Centurelli, Valerio Spinogatti, Alessandro Trifiletti
2023 J jnl
A body-driven rail-to-rail 0.3 V operational transconductance amplifier exploiting current gain stages.
Int. J. Circuit Theory Appl.
Riccardo Della Sala, Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
2023 J jnl
An Improved Strong Arm Comparator With Integrated Static Preamplifier.
IEEE Access
Valerio Spinogatti, Riccardo Della Sala, Cristian Bocciarelli, Francesco Centurelli, Alessandro Trifiletti
2023 — conf
CMOS Adaptive Biased Second Generation Voltage Conveyor.
BATS
Gianluca Barile, Vincenzo Stornelli, Leonardo Pantoli, Davide Colaiuda, Francesco Centurelli, Pasquale Tommasino, Alessandro Trifiletti, Giuseppe Ferri
2023 J jnl
High-Accuracy Low-Cost Generalized Complex Pruned Volterra Models for Nonlinear Calibration.
IEEE Trans. Circuits Syst. I Regul. Pap.
Cristian Bocciarelli, Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Valerio Spinogatti, Pasquale Tommasino, Alessandro Trifiletti
2023 — conf
Robust Body Biasing Techniques for Dynamic Comparators.
PRIME
Valerio Spinogatti, Cristian Bocciarelli, Francesco Centurelli, Riccardo Della Sala, Alessandro Trifiletti
2022 J jnl
A SiGe HBT 6th-Order 10 GHz Inductor-Less Anti-Aliasing Low-Pass Filter for High-Speed ATI Digitizers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Pasquale Tommasino, Alessandro Trifiletti
2022 J jnl
General Approach to the Calibration of Innovative MFP Multichannel Digitizers.
IEEE Trans. Instrum. Meas.
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti, Mauro D'Arco, Leopoldo Angrisani
2021 J jnl
A Detailed Model of the Switched-Resistor Technique.
IEEE Open J. Circuits Syst.
Francesco Centurelli, Alessandro Fava, Giuseppe Scotti, Alessandro Trifiletti
2021 C conf
A Low-Voltage High-Performance Frequency Divider exploiting Folded MCML.
ISCAS
Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo
2021 J jnl
Compact E-Band I/Q Receiver in SiGe BiCMOS for 5G Backhauling Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Giandomenico Amendola, Luigi Boccia, Francesco Centurelli, Pascal Chevalier, Alessandro Fonte, Carmine Mustacchio, Andrea Pallotta, Pasquale Tommasino, Antonio Traversa, Alessandro Trifiletti
2021 J jnl
Design of Low-Voltage Power Efficient Frequency Dividers in Folded MOS Current Mode Logic.
IEEE Trans. Circuits Syst. I Regul. Pap.
Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo
2020 J jnl
0.6-V CMOS cascode OTA with complementary gate-driven gain-boosting and forward body bias.
Int. J. Circuit Theory Appl.
Danilo Cellucci, Francesco Centurelli, Valerio Di Stefano, Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2020 J jnl
A Novel 0.5 V MCML D-Flip-Flop Topology Exploiting Forward Body Bias Threshold Lowering.
IEEE Trans. Circuits Syst. II Express Briefs
Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo
2020 J jnl
An improved reversed miller compensation technique for three-stage CMOS OTAs with double pole-zero cancellation and almost single-pole frequency response.
Int. J. Circuit Theory Appl.
Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Pasquale Tommasino, Alessandro Trifiletti
2020 J jnl
Delay models and design guidelines for MCML gates with resistor or PMOS load.
Microelectron. J.
Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo
2020 — conf
High-speed AWG exploiting parallel time interleaved DAC cores.
I2MTC
Mauro D'Arco, Leopoldo Angrisani, Pietro Monsurrò, Alessandro Trifiletti
2020 J jnl
Low-power class-AB 4th-order low-pass filter based on current conveyors with dynamic mismatch compensation of biasing errors.
Int. J. Circuit Theory Appl.
Francesco Centurelli, Pietro Monsurrò, Vincenzo Stornelli, Gianluca Barile, Alessandro Trifiletti
2019 — conf
A low-power class-AB Gm-C biquad stage in CMOS 40nm technology.
ICECS
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2019 — conf
Area-Efficient Low-Power Bandpass Gm-C Filter for Epileptic Seizure Detection in 130nm CMOS.
ICECS
Riccardo Della Sala, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
2019 J jnl
High-gain, high-CMRR class AB operational transconductance amplifier based on the flipped voltage follower.
Int. J. Circuit Theory Appl.
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2018 — conf
A Novel 0.6V MCML D-Latch Topology exploiting Dynamic Body Bias Threshold Lowering.
ICECS
Giuseppe Scotti, Alessandro Trifiletti, Gaetano Palumbo
2018 — conf
A Novel Very Low Voltage Topology to implement MCML XOR Gates.
PRIME
Davide Bellizia, Gaetano Palumbo, Giuseppe Scotti, Alessandro Trifiletti
2018 J jnl
A Topology of Fully Differential Class-AB Symmetrical OTA With Improved CMRR.
IEEE Trans. Circuits Syst. II Express Briefs
Francesco Centurelli, Pietro Monsurrò, Gaetano Parisi, Pasquale Tommasino, Alessandro Trifiletti
2018 J jnl
New Models for the Calibration of Four-Channel Time-Interleaved ADCs Using Filter Banks.
IEEE Trans. Circuits Syst. II Express Briefs
Pietro Monsurrò, Felice Rosato, Alessandro Trifiletti
2018 J jnl
Secure Double Rate Registers as an RTL Countermeasure Against Power Analysis Attacks.
IEEE Trans. Very Large Scale Integr. Syst.
Davide Bellizia, Simone Bongiovanni, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti, Francesco Bruno Trotta
2018 C conf
Secure Implementation of TEL-compatible Flip-Flops using a Standard-Cell Approach.
ISCAS
Davide Bellizia, Giuseppe Scotti, Alessandro Trifiletti
2018 J jnl
TEL Logic Style as a Countermeasure Against Side-Channel Attacks: Secure Cells Library in 65nm CMOS and Experimental Results.
IEEE Trans. Circuits Syst. I Regul. Pap.
Davide Bellizia, Giuseppe Scotti, Alessandro Trifiletti
2017 J jnl
0.9-V Class-AB Miller OTA in 0.35-µm CMOS With Threshold-Lowered Non-Tailed Differential Pair.
IEEE Trans. Circuits Syst. I Regul. Pap.
Alfio Dario Grasso, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2017 J jnl
A Novel Framework to Estimate the Path Delay Variability On the Back of an Envelope via the Fan-Out-of-4 Metric.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Giuseppe Scotti, Alessandro Trifiletti
2017 — conf
A fully-differential class-AB OTA with CMRR improved by local feedback.
ECCTD
Francesco Centurelli, Pietro Monsurrò, Gaetano Parisi, Pasquale Tommasino, Alessandro Trifiletti
2017 J jnl
Calibration of Time-Interleaved ADCs via Hermitianity-Preserving Taylor Approximations.
IEEE Trans. Circuits Syst. II Express Briefs
Pietro Monsurrò, Alessandro Trifiletti
2017 — conf
Class-AB current conveyors based on the FVF.
ECCTD
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti, Gianluca Barile, Giuseppe Ferri, Leonardo Pantoli, Vincenzo Stornelli
2017 J jnl
Design of Low-Voltage High-Speed CML D-Latches in Nanometer CMOS Technologies.
IEEE Trans. Very Large Scale Integr. Syst.
Giuseppe Scotti, Davide Bellizia, Alessandro Trifiletti, Gaetano Palumbo
2017 C conf
Design-oriented models for quick estimation of path delay variability via the fan-out-of-4 metric.
ISCAS
Massimo Alioto, Giuseppe Scotti, Alessandro Trifiletti
2017 J jnl
Faster, Stabler, and Simpler - A Recursive-Least-Squares Algorithm Exploiting the Frisch-Waugh-Lovell Theorem.
IEEE Trans. Circuits Syst. II Express Briefs
Pietro Monsurrò, Alessandro Trifiletti
2017 J jnl
Fully Differential Class-AB OTA with Improved CMRR.
J. Circuits Syst. Comput.
Francesco Centurelli, Pietro Monsurrò, Gaetano Parisi, Pasquale Tommasino, Alessandro Trifiletti
2017 — conf
Multi-rate signal processing based model for high-speed digitizers.
I2MTC
Pietro Monsurrò, Alessandro Trifiletti, Leopoldo Angrisani, Mauro D'Arco
2017 — conf
Multivariate Analysis Exploiting Static Power on Nanoscale CMOS Circuits for Cryptographic Applications.
AFRICACRYPT
Milena Djukanovic, Davide Bellizia, Giuseppe Scotti, Alessandro Trifiletti
2017 — conf
Novel measurements setup for attacks exploiting static power using DC pico-ammeter.
ECCTD
Davide Bellizia, Danilo Cellucci, Valerio Di Stefano, Giuseppe Scotti, Alessandro Trifiletti
2017 — conf
On the use of voltage conveyors for the synthesis of biquad filters and arbitrary networks.
ECCTD
Francesco Centurelli, Pietro Monsurrò, Pasquale Tommasino, Alessandro Trifiletti
2017 — conf
Perfect reconstruction filters for 4-channels time-interleaved ADC affected by mismatches.
ECCTD
Felice Rosato, Pietro Monsurrò, Alessandro Trifiletti
2017 — conf
Power-efficient dynamic-biased CCII.
ECCTD
Gianluca Barile, L. Liberati, Giuseppe Ferri, Leonardo Pantoli, Vincenzo Stornelli, Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2017 J jnl
Template attacks exploiting static power and application to CMOS lightweight crypto-hardware.
Int. J. Circuit Theory Appl.
Davide Bellizia, Milena Djukanovic, Giuseppe Scotti, Alessandro Trifiletti
2017 — conf
The recursive batch least squares filter: An efficient RLS filter for floating-point hardware.
ECCTD
Pietro Monsurrò, Alessandro Trifiletti
2017 J jnl
Univariate Power Analysis Attacks Exploiting Static Dissipation of Nanometer CMOS VLSI Circuits for Cryptographic Applications.
IEEE Trans. Emerg. Top. Comput.
Davide Bellizia, Simone Bongiovanni, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
2017 — conf
VHDL implementation of FWL RLS algorithm.
ECCTD
Davide Bellizia, Pietro Monsurrò, Alessandro Trifiletti
2016 — conf
A fault-tolerant real-time microcontroller with multiprocessor architecture.
MIXDES
Elio Strollo, Alessandro Trifiletti
2016 — conf
A new class-AB Flipped Voltage Follower using a common-gate auxiliary amplifier.
MIXDES
Francesco Centurelli, Pietro Monsurrò, Danilo Ruscio, Alessandro Trifiletti
2016 — conf
A shared memory, parameterized and configurable in FPGA, for use in multiprocessor systems.
MIXDES
Elio Strollo, Alessandro Trifiletti
2016 J jnl
CMOS Non-tailed differential pair.
Int. J. Circuit Theory Appl.
Giuseppe Di Cataldo, Alfio Dario Grasso, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2016 J jnl
Comparative performance analysis and complementary triode based CMFB circuits for fully differential class AB symmetrical OTAs with low power consumption.
Int. J. Circuit Theory Appl.
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2016 — conf
Implementation of the PRESENT-80 block cipher and analysis of its vulnerability to Side Channel Attacks Exploiting Static Power.
MIXDES
Davide Bellizia, Giuseppe Scotti, Alessandro Trifiletti
2016 — conf
On-chip analog current equalizer as a countermeasure against side-channel attacks in CMOS nanometer technology.
MIXDES
Davide Bellizia, Giuseppe Scotti, Alessandro Trifiletti
2016 — conf
Synthesis of anti-aliasing filters for IF receivers.
MIXDES
Pietro Monsurrò, Alessandro Trifiletti
2015 J jnl
Design and validation through a frequency-based metric of a new countermeasure to protect nanometer ICs from side-channel attacks.
J. Cryptogr. Eng.
Simone Bongiovanni, Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti
2015 J jnl
High-tuning-range CMOS band-pass IF filter based on a low-
Int. J. Circuit Theory Appl.
Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2015 J jnl
Subsampling Models of Bandwidth Mismatch for Time-Interleaved Converter Calibration.
IEEE Trans. Circuits Syst. II Express Briefs
Pietro Monsurrò, Alessandro Trifiletti
2014 J jnl
88-µ A 1-MHz Stray-Insensitive CMOS Current-Mode Interface IC for Differential Capacitive Sensors.
IEEE Trans. Circuits Syst. I Regul. Pap.
Giuseppe Scotti, Salvatore Pennisi, Pietro Monsurrò, Alessandro Trifiletti
2014 B conf
A Novel Wake-Up Receiver with Addressing Capability for Wireless Sensor Nodes.
DCOSS
Chiara Petrioli, Dora Spenza, Pasquale Tommasino, Alessandro Trifiletti
2014 J jnl
A wideband amplifier topology based on positive capacitive feedback.
Microelectron. J.
Francesco Centurelli, Roberto Antonio Gualano, Alessandro Trifiletti
2014 — conf
Architecture and modeling of a novel optical beamforming network suitable for microwave photonics implementation.
MIXDES
Pietro Monsurrò, Pasquale Tommasino, Alessandro Trifiletti, Gianpietro Locatelli, Antonello Vannucci
2014 — conf
Design of broad-band power amplifiers by means of an impedance transforming lossy equalizer.
MIXDES
Francesco Centurelli, Giuseppe Scotti, Pasquale Tommasino, Alessandro Trifiletti, Milena Djukanovic
2014 J jnl
Effectiveness of Leakage Power Analysis Attacks on DPA-Resistant Logic Styles Under Process Variations.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Simone Bongiovanni, Milena Djukanovic, Giuseppe Scotti, Alessandro Trifiletti
2014 — conf
Experiments on two clock countermeasures against power analysis attacks.
MIXDES
Renato Menicocci, Alessandro Trifiletti, Francesco Bruno Trotta
2014 — conf
Implementing radar algorithms on CUDA hardware.
MIXDES
Pietro Monsurrò, Alessandro Trifiletti, Francesco Lannutti
2014 — conf
Leakage Power Analysis attacks against a bit slice implementation of the Serpent block cipher.
MIXDES
Massimo Alioto, Simone Bongiovanni, Giuseppe Scotti, Alessandro Trifiletti
2013 — conf
A flip-flop implementation for the DPA-resistant Delay-based Dual-rail Pre-charge Logic family.
MIXDES
Simone Bongiovanni, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
2013 — conf
A logic level countermeasure against CPA side channel attacks on AES.
MIXDES
Renato Menicocci, Alessandro Trifiletti, Francesco Bruno Trotta
2013 J jnl
Adaptive frequency compensation for maximum and constant bandwidth feedback amplifiers.
Int. J. Circuit Theory Appl.
Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2013 — conf
Effect of components relative tolerance in the magnitude response of a Gm-C biquad.
ECCTD
Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti, Salvatore Pennisi
2013 J jnl
Improved Digital Background Calibration of Time-Interleaved Pipeline A/D Converters.
IEEE Trans. Circuits Syst. II Express Briefs
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2013 C conf
Security Evaluation and Optimization of the Delay-based Dual-rail Pre-charge Logic in Presence of Early Evaluation of Data.
SECRYPT
Simone Bongiovanni, Giuseppe Scotti, Alessandro Trifiletti
2012 J jnl
A Flip-Flop for the DPA Resistant Three-Phase Dual-Rail Pre-Charge Logic Family.
IEEE Trans. Very Large Scale Integr. Syst.
Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti
2012 C conf
Autotuning technique for CMOS current mode capacitive sensor interfaces.
ISCAS
Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2012 C conf
Constant and maximum bandwidth feedback amplifier with adaptive frequency compensation.
ISCAS
Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2012 J jnl
Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2011 — conf
A class-AB flipped voltage follower output stage.
ECCTD
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2011 — conf
A class-AB very low voltage amplifier and sample & hold circuit.
ECCTD
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2011 — conf
A very low-voltage differential amplifier for opamp design.
ECCTD
Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
2011 — conf
An MDAC architecture with low sensitivity to finite opamp gain.
ECCTD
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2011 J jnl
Avoiding the Gain-Bandwidth Trade Off in Feedback Amplifiers.
IEEE Trans. Circuits Syst. I Regul. Pap.
Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2011 J jnl
Delay-Based Dual-Rail Precharge Logic.
IEEE Trans. Very Large Scale Integr. Syst.
Marco Bucci, Luca Giancane, Raimondo Luzzi, Giuseppe Scotti, Alessandro Trifiletti
2011 — conf
Design strategy for biquad-based continuous-time low-pass filters.
ECCTD
Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2011 C conf
Leakage Power Analysis attacks: Effectiveness on DPA resistant logic styles under process variations.
ISCAS
Milena Djukanovic, Luca Giancane, Giuseppe Scotti, Alessandro Trifiletti, Massimo Alioto
2011 J jnl
Reply to "Comments on Avoiding the Gain-Bandwidth Trade Off in Feedback Amplifiers".
IEEE Trans. Circuits Syst. I Regul. Pap.
Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2010 J jnl
Behavioral Modeling for Calibration of Pipeline Analog-To-Digital Converters.
IEEE Trans. Circuits Syst. I Regul. Pap.
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2010 J jnl
Leakage Power Analysis Attacks: A Novel Class of Attacks to Nanometer Cryptographic Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Massimo Alioto, Luca Giancane, Giuseppe Scotti, Alessandro Trifiletti
2010 C conf
On Practical Second-Order Power Analysis Attacks for Block Ciphers.
ICICS
Renato Menicocci, Andrea Simonetti, Giuseppe Scotti, Alessandro Trifiletti
2009 J jnl
0.9-V CMOS cascode amplifier with body-driven gain boosting.
Int. J. Circuit Theory Appl.
Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2009 J jnl
A novel low-voltage low-power fully differential voltage and current gained CCII for floating impedance simulations.
Microelectron. J.
Andrea De Marcellis, Giuseppe Ferri, Nicola Carlo Guerrini, Giuseppe Scotti, Vincenzo Stornelli, Alessandro Trifiletti
2009 J jnl
Analysis and Implementation of a Minimum-Supply Body-Biased CMOS Differential Amplifier Cell.
IEEE Trans. Very Large Scale Integr. Syst.
Alfio Dario Grasso, Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2009 C conf
CMOS Body-enhanced Cascode Current Mirror.
ISCAS
Carmine Gianni, Giuseppe Scotti, Alessandro Trifiletti, Salvatore Pennisi
2009 — conf
Delay-based dual-rail pre-charge logic.
ICECS
Marco Bucci, Luca Giancane, Raimondo Luzzi, Giuseppe Scotti, Alessandro Trifiletti
2009 J jnl
Design Solutions for Sample-and-Hold Circuits in CMOS Nanometer Technologies.
IEEE Trans. Circuits Syst. II Express Briefs
Francesco Centurelli, Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2009 — conf
Leakage Power Analysis attacks: Theoretical analysis and impact of variations.
ICECS
Massimo Alioto, Luca Giancane, Giuseppe Scotti, Alessandro Trifiletti
2009 C conf
Power Analysis of a Chaos-based Random Number Generator for Cryptographic Security.
ISCAS
Fabio Pareschi, Giuseppe Scotti, Luca Giancane, Riccardo Rovatti, Gianluca Setti, Alessandro Trifiletti
2008 J jnl
A Simple Technique for Fast Digital Background Calibration of A/D Converters.
EURASIP J. Adv. Signal Process.
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2008 C conf
A gain-enhancing technique for very low-voltage amplifiers.
ISCAS
Francesco Centurelli, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
2008 — conf
A new dynamic differential logic style as a countermeasure to power analysis attacks.
ICECS
Luca Giancane, Piero Marietti, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
2008 — conf
Differential Capacitance Analysis.
PATMOS
Marco Bucci, Raimondo Luzzi, Giuseppe Scotti, Andrea Simonetti, Alessandro Trifiletti
2008 C conf
Dual op amp, LDO regulator with power supply gain suppression for CMOS smart sensors and microsystems.
ISCAS
Christian Falconi, Arnaldo D'Amico, Giuseppe Scotti, Alessandro Trifiletti
2008 J jnl
Enhancing power analysis attacks against cryptographic devices.
IET Circuits Devices Syst.
Marco Bucci, Luca Giancane, Raimondo Luzzi, M. Marino, Giuseppe Scotti, Alessandro Trifiletti
2008 J jnl
High-Level Side-Channel Attack Modeling and Simulation for Security-Critical Systems on Chips.
IEEE Trans. Dependable Secur. Comput.
Francesco Menichelli, Renato Menicocci, Mauro Olivieri, Alessandro Trifiletti
2008 C conf
Low voltage, low power, compact, high accuracy, high precision PTAT temperature sensor for deep sub-micron CMOS systems.
ISCAS
Christian Falconi, Marco Fratini, Arnaldo D'Amico, Giuseppe Scotti, Alessandro Trifiletti
2008 C conf
Mixed-signal flexible architecture for the synthesis of n-port networks.
ISCAS
Carmine Gianni, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2008 J jnl
Unity-Gain Amplifier With Theoretically Zero Gain Error.
IEEE Trans. Instrum. Meas.
Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2007 C conf
150 µA CMOS Transconductor with 82 dB SFDR.
ISCAS
Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2007 J jnl
A Dynamic and Differential CMOS Lookup Table with Data-Independent Power Consumption for Cryptographic Applications on Chip Cards.
IEEE Trans. Dependable Secur. Comput.
Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti
2007 J jnl
A High-Speed Low-Voltage Phase Detector for Clock Recovery From NRZ Data.
IEEE Trans. Circuits Syst. I Regul. Pap.
Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti
2007 — conf
A Sample-and-Hold Circuit with Very Low Gain Error for Time Interleaving Applications.
ECCTD
Francesco Centurelli, Andrea Simonetti, Alessandro Trifiletti
2007 — conf
A Statistical Model of Logic Gates for Monte Carlo Simulation Including On-Chip Variations.
PATMOS
Francesco Centurelli, Luca Giancane, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
2007 C conf
A distortion model for pipeline Analog-to-Digital converters.
ISCAS
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2007 — conf
Analysis of data dependence of leakage current in CMOS cryptographic hardware.
ACM Great Lakes Symposium on VLSI
Jacopo Giorgetti, Giuseppe Scotti, Andrea Simonetti, Alessandro Trifiletti
2007 — conf
CCII-based high-valued inductance simulators with minumum number of active elements.
ECCTD
Giuseppe Ferri, Nicola Carlo Guerrini, R. Romanato, Giuseppe Scotti, Alessandro Trifiletti
2007 J jnl
CMOS High-CMRR Current Output Stages.
IEEE Trans. Circuits Syst. II Express Briefs
Francesco Centurelli, Alfio Dario Grasso, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2007 — conf
CMOS Miller OTA with Body-Biased Output Stage.
ECCTD
Alfio Dario Grasso, Salvatore Pennisi, Francesco Centurelli, Giuseppe Scotti, Alessandro Trifiletti
2007 J jnl
Linearization Technique for Source-Degenerated CMOS Differential Transconductors.
IEEE Trans. Circuits Syst. II Express Briefs
Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2007 C conf
Low Voltage CMOS Current and Voltage References without Resistors.
ISCAS
Christian Falconi, Arnaldo D'Amico, Giuseppe Scotti, Alessandro Trifiletti
2007 — conf
Mismatch Tolerant, Continuous Time, Rail to Rail, Gain Enhanced CMOS Amplifiers.
ECCTD
M. Cianella, Christian Falconi, Arnaldo D'Amico, Giuseppe Scotti, Alessandro Trifiletti
2007 C conf
Mismatch-tolerant, Continuous Time, Gain Enhanced Amplifiers.
ISCAS
Christian Falconi, M. Cianella, Arnaldo D'Amico, Giuseppe Scotti, Alessandro Trifiletti
2007 — conf
Power-constrained Bandwidth Optimization in Cascaded Open-loop Amplifiers.
ECCTD
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2007 C conf
Source-degenerated CMOS Transconductor with Auxiliary Linearization.
ISCAS
Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti, Salvatore Pennisi
2007 — conf
Sub-1V CMOS OTA with Body-driven Gain Boosting.
ECCTD
Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti, Salvatore Pennisi
2007 J jnl
Testing power-analysis attack susceptibility in register-transfer level designs.
IET Inf. Secur.
Marco Bucci, Raimondo Luzzi, Francesco Menichelli, Renato Menicocci, Mauro Olivieri, Alessandro Trifiletti
2007 J jnl
The Universal Circuit Simulator: A Mixed-Signal Approach to n-Port Network and Impedance Synthesis.
IEEE Trans. Circuits Syst. I Regul. Pap.
Carmine Gianni, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2007 — conf
Very Low Voltage CMOS Two-stage Amplifier.
ECCTD
Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti, Salvatore Pennisi
2006 C conf
A model for the distortion due to switch on-resistance in sample-and-hold circuits.
ISCAS
Francesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti
2006 C conf
A novel concept for stateless random bit generators in cryptographic applications.
ISCAS
Marco Bucci, Luca Giancane, Raimondo Luzzi, Mario Varanonuovo, Alessandro Trifiletti
2006 C conf
Enhancing power analysis attacks against cryptographic devices.
ISCAS
Marco Bucci, Luca Giancane, Raimondo Luzzi, Giuseppe Scotti, Alessandro Trifiletti
2006 J jnl
High-CMRR Current Amplifier Architecture and Its CMOS Implementation.
IEEE Trans. Circuits Syst. II Express Briefs
Salvatore Pennisi, Mauro Piccioni, Giuseppe Scotti, Alessandro Trifiletti
2006 C conf
Inverting closed-loop amplifier architecture with reduced gain error and high input impedance.
ISCAS
Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2006 C conf
Side channel analysis resistant design flow.
ISCAS
Manfred Josef Aigner, Stefan Mangard, Francesco Menichelli, Renato Menicocci, Mauro Olivieri, Thomas Popp, Giuseppe Scotti, Alessandro Trifiletti
2006 A conf
Three-Phase Dual-Rail Pre-charge Logic.
CHES
Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti
2006 C conf
Validation of a statistical non-linear model of GaAs HEMT MMIC's by hypothesis testing and principal components analysis.
ISCAS
Marco Balsi, Francesco Centurelli, Piero Marietti, Giuseppe Scotti, Pasquale Tommasino, Alessandro Trifiletti, Giancarlo Valente
2005 — conf
10-th order programmable low-pass CMOS integrated pulse-shaping filter.
ISCAS (4)
Marco Balsi, Nicola Carlo Guerrini, Piero Marietti, Giuseppe Scotti, G. Stochino, Alessandro Trifiletti
2005 — conf
2-V CMOS current operational amplifier with high CMRR.
ECCTD
Raimondo Luzzi, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2005 J jnl
A 10-Gb/s CMU/CDR chip-set in SiGe BiCMOS commercial technology with multistandard capability.
IEEE Trans. Very Large Scale Integr. Syst.
Francesco Centurelli, Alessandro Golfarelli, Jesus Guinea, Leonardo Masini, Damiana Morigi, Massimo Pozzoni, Giuseppe Scotti, Alessandro Trifiletti
2005 — conf
A countermeasure against differential power analysis based on random delay insertion.
ISCAS (4)
Marco Bucci, Raimondo Luzzi, Michele Guglielmo, Alessandro Trifiletti
2005 — conf
A novel CMOS logic style with data independent power consumption.
ISCAS (2)
Manfred Josef Aigner, Stefan Mangard, Renato Menicocci, Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
2005 J jnl
A novel yield optimization technique for digital CMOS circuits design by means of process parameters run-time estimation and body bias active control.
IEEE Trans. Very Large Scale Integr. Syst.
Mauro Olivieri, Giuseppe Scotti, Alessandro Trifiletti
2005 J jnl
Analytic transient solution of SCFL logic gates.
Int. J. Circuit Theory Appl.
Alberto Maria Bersani, Francesco Centurelli, Luca Fontana, Alessandro Trifiletti
2005 — conf
CMOS single-to-differential current amplifier.
ISCAS (3)
Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2005 J jnl
Design and Test of a Novel Programmable Clock Generator Semi-Custom Core for Energy-Efficient Systems-on-Chips.
J. Low Power Electron.
Mauro Olivieri, Simone Smorfa, Alessandro Trifiletti
2005 — conf
High-speed CMOS-to-ECL pad driver in 0.18µm CMOS.
ISCAS (1)
Francesco Centurelli, G. Lulli, Piero Marietti, Pietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti
2005 — conf
Optimized design of source coupled logic gates in GaAs HEMT technology.
ISCAS (4)
Gaetano Palumbo, Pasquale Tommasino, Alessandro Trifiletti
2005 — conf
Switched-capacitor body-biasing technique for very low voltage CMOS amplifiers.
ECCTD
Pietro Monsurrò, Salvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti
2004 — conf
A Power Consumption Randomization Countermeasure for DPA-Resistant Cryptographic Processors.
PATMOS
Marco Bucci, Michele Guglielmo, Raimondo Luzzi, Alessandro Trifiletti
2004 — conf
A high-speed low-voltage phase detector for clock recovery from NRZ data.
ISCAS (4)
Francesco Centurelli, Massimo Pozzoni, Giuseppe Scotti, Alessandro Trifiletti
2004 — conf
Robust three-state PFD architecture with enhanced frequency acquisition capabilities.
ISCAS (4)
Francesco Centurelli, Stefano Costi, Mauro Olivieri, Salvatore Pennisi, Alessandro Trifiletti
2004 — conf
Yield Optimization by Means of Process Parameters Estimation: Comparison Between ABB and ASV Techniques.
PATMOS
Mauro Olivieri, Mirko Scarana, Giuseppe Scotti, Alessandro Trifiletti
2003 J jnl
A High-Speed Oscillator-Based Truly Random Number Source for Cryptographic Applications on a Smart Card IC.
IEEE Trans. Computers
Marco Bucci, Lucia Germani, Raimondo Luzzi, Alessandro Trifiletti, Mario Varanonuovo
2003 — conf
A charge injection based CMOS charge-pump.
ICECS
Marco Bucci, Raimondo Luzzi, Salvatore Pennisi, Alessandro Trifiletti
2003 — conf
An accurate behavioral model of phase detectors for clock recovery circuits.
ISCAS (4)
Marco Balsi, Francesco Centurelli, Giuseppe Scotti, Pasquale Tommasino, Alessandro Trifiletti
2003 — conf
Current output stage with improved CMRR.
ICECS
Francesco Centurelli, Salvatore Pennisi, Alessandro Trifiletti
2002 — conf
A high speed truly IC random number source for smart card microcontrollers.
ICECS
Marco Bucci, Lucia Germani, Raimondo Luzzi, Pasquale Tommasino, Alessandro Trifiletti, Mario Varanonuovo
2002 — conf
A tree-like amplifier architecture for large gain-bandwidth product.
ICECS
Marco Balsi, Francesco Centurelli, Salvatore Pennisi, Alessandro Trifiletti
2002 — conf
Bipolar differential cell with improved bandwidth performance.
ICECS
Marco Balsi, Francesco Centurelli, Salvatore Pennisi, Alessandro Trifiletti
2001 — conf
An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores.
ISCAS (4)
Mauro Olivieri, Alessandro Trifiletti
2000 A conf
A low-power clock and data recovery circuit for 2.5 Gb/s SDH receivers.
ISLPED
Andrea Pallotta, Francesco Centurelli, Alessandro Trifiletti
1999 C conf
A Low-Power Microcontroller with on-Chip Self-Tuning Digital Clock-Generator for Variable-Load Applications.
ICCD
Mauro Olivieri, Alessandro Trifiletti, Alessandro De Gloria
1998 — conf
A monolithic 2.5-Gb/s clock and data recovery circuit based on Silicon bipolar technology.
Broadband European Networks and Multimedia Services
Andrea Pallotta, Francesco Centurelli, Francesco Loriga, Alessandro Trifiletti