Alessandro Tempia Calvino

24 papers A* 2A 4B 2C 3Journal 5Unranked 7
YearRankTypeTitle / Venue / Authors
2025 — conf
Area-Oriented Optimization After Standard-Cell Mapping.
ASP-DAC
Andrea Costamagna, Alessandro Tempia Calvino, Alan Mishchenko, Giovanni De Micheli
2025 J jnl
Area-Oriented Resubstitution For Networks of Look-Up Tables.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Andrea Costamagna, Alessandro Tempia Calvino, Alan Mishchenko, Giovanni De Micheli
2025 — conf
Back-end-aware Fault-tolerant Quantum Oracle Synthesis.
ASP-DAC
Mingfei Yu, Alessandro Tempia Calvino, Mathias Soeken, Giovanni De Micheli
2025 J jnl
Enhancing Delay-Driven LUT Mapping With Boolean Decomposition.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Alessandro Tempia Calvino, Giovanni De Micheli, Alan Mishchenko, Robert K. Brayton
2025 J jnl
Technology Legalization and Optimization for Adiabatic Quantum-Flux Parametron.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Siang-Yun Lee, Alessandro Tempia Calvino, Heinz Riener, Giovanni De Micheli
2024 B conf
Algebraic and Boolean Methods for SFQ Superconducting Circuits.
ASPDAC
Alessandro Tempia Calvino, Giovanni De Micheli
2024 B conf
In Medio Stat Virtus*: Combining Boolean and Pattern Matching.
ASPDAC
Gianluca Radi, Alessandro Tempia Calvino, Giovanni De Micheli
2024 A* conf
Late Breaking Results: Majority-Inverter Graph Minimization by Design Space Exploration.
DAC
Siang-Yun Lee, Alessandro Tempia Calvino, Heinz Riener, Giovanni De Micheli
2024 — conf
On the Synthesis of High-performance Homomorphic Boolean Circuits.
WAHC@CCS
Mingfei Yu, Sergiu Carpov, Alessandro Tempia Calvino, Giovanni De Micheli
2024 J jnl
Practical Boolean Decomposition for Delay-driven LUT Mapping.
CoRR
Alessandro Tempia Calvino, Alan Mishchenko, Giovanni De Micheli, Robert K. Brayton
2024 A conf
Scalable Logic Rewriting Using Don't Cares.
DATE
Alessandro Tempia Calvino, Giovanni De Micheli
2024 — —
Technology Mapping and Optimization Algorithms for Logic Synthesis of Advanced Technologies.
Alessandro Tempia Calvino
2024 A conf
Technology-Aware Logic Synthesis for Superconducting Electronics.
DATE
Rassul Bairamkulov, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Mingfei Yu, Giovanni De Micheli
2023 — conf
Depth-Optimal Buffer and Splitter Insertion and Optimization in AQFP Circuits.
ASP-DAC
Alessandro Tempia Calvino, Giovanni De Micheli
2023 A* conf
Improving Standard-Cell Design Flow using Factored Form Optimization.
DAC
Alessandro Tempia Calvino, Alan Mishchenko, Herman Schmit, Ethan Mahintorabi, Giovanni De Micheli, Xiaoqing Xu
2023 C conf
Synthesis of SFQ Circuits with Compound Gates.
VLSI-SoC
Rassul Bairamkulov, Alessandro Tempia Calvino, Giovanni De Micheli
2023 — conf
Synthesis of SFQ Circuits with Compound Gates.
VLSI-SoC (Selected Papers)
Rassul Bairamkulov, Alessandro Tempia Calvino, Giovanni De Micheli
2023 A conf
Technology Mapping Using Multi-Output Library Cells.
ICCAD
Alessandro Tempia Calvino, Giovanni De Micheli
2023 J jnl
Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Shubham Rai, Alessandro Tempia Calvino, Heinz Riener, Giovanni De Micheli, Akash Kumar
2022 — conf
A Versatile Mapping Approach for Technology Mapping and Graph Optimization.
ASP-DAC
Alessandro Tempia Calvino, Heinz Riener, Shubham Rai, Akash Kumar, Giovanni De Micheli
2022 — conf
Dependency Graphs to Boost the Verification of SysML Models.
MODELSWARD (Revised Selected Papers)
Ludovic Apvrille, Pierre de Saqui-Sannes, Oana Hotescu, Alessandro Tempia Calvino
2022 A conf
Majority-based Design Flow for AQFP Superconducting Family.
DATE
Giulia Meuli, Vinicius N. Possani, Rajinder Singh, Siang-Yun Lee, Alessandro Tempia Calvino, Dewmini Sudara Marakkalage, Patrick Vuillod, Luca G. Amarù, Scott Chase, Jamil Kawa, Giovanni De Micheli
2022 C conf
SysML Models Verification Relying on Dependency Graphs.
MODELSWARD
Ludovic Apvrille, Pierre de Saqui-Sannes, Oana Hotescu, Alessandro Tempia Calvino
2021 C conf
Direct Model-checking of SysML Models.
MODELSWARD
Alessandro Tempia Calvino, Ludovic Apvrille