Alessandro Ottaviano

35 papers A 4C 1Journal 26Unranked 4
YearRankTypeTitle / Venue / Authors
2025 J jnl
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications.
CoRR
Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025 J jnl
A Reliable, Time-Predictable Heterogeneous SoC for AI-Enhanced Mixed-Criticality Edge Applications.
IEEE Trans. Circuits Syst. II Express Briefs
Angelo Garofalo, Alessandro Ottaviano, Matteo Perotti, Thomas Benz, Yvan Tortorella, Robert Balas, Michael Rogenmoser, Chi Zhang, Luca Bertaccini, Nils Wistoff, Maicol Ciani, Cyril Koenig, Mattia Sinigaglia, Luca Valente, Paul Scheffler, Manuel Eggimann, Matheus A. Cavalcante, Francesco Restuccia, Alessandro Biondi, Francesco Conti, Frank K. Gürkaynak, Davide Rossi, Luca Benini
2025 J jnl
AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems.
CoRR
Thomas Benz, Alessandro Ottaviano, Chaoqun Liang, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Davide Rossi, Luca Benini
2025 J jnl
AXI-REALM: Safe, Modular and Lightweight Traffic Monitoring and Regulation for Heterogeneous Mixed-Criticality Systems.
IEEE Trans. Computers
Thomas Benz, Alessandro Ottaviano, Chaoqun Liang, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Davide Rossi, Luca Benini
2025 — conf
CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor.
CF
Christopher Reinwardt, Robert Balas, Alessandro Ottaviano, Angelo Garofalo, Luca Benini
2025 J jnl
CVA6-VMRT: A Modular Approach Towards Time-Predictable Virtual Memory in a 64-bit Application Class RISC-V Processor.
CoRR
Christopher Reinwardt, Robert Balas, Alessandro Ottaviano, Angelo Garofalo, Luca Benini
2025 J jnl
Co-designing a Programmable RISC-V Accelerator for MPC-based Energy and Thermal Management of Many-Core HPC Processors.
CoRR
Alessandro Ottaviano, Andrino Meli, Paul Scheffler, Giovanni Bambini, Robert Balas, Davide Rossi, Andrea Bartolini, Luca Benini
2025 J jnl
ControlPULPlet: A Flexible Real-time Multicore RISC-V Controller for 2.5-D Systems-in-Package.
IEEE Trans. Very Large Scale Integr. Syst.
Alessandro Ottaviano, Robert Balas, Tim Fischer, Thomas Benz, Andrea Bartolini, Luca Benini
2025 A conf
Towards Reliable Systems: A Scalable Approach to AXI4 Transaction Monitoring.
DATE
Chaoqun Liang, Thomas Benz, Alessandro Ottaviano, Angelo Garofalo, Luca Benini, Davide Rossi
2025 J jnl
Towards Reliable Systems: A Scalable Approach to AXI4 Transaction Monitoring.
CoRR
Chaoqun Liang, Thomas Benz, Alessandro Ottaviano, Angelo Garofalo, Luca Benini, Davide Rossi
2024 — conf
A Gigabit, DMA-enhanced Open-Source Ethernet Controller for Mixed-Criticality Systems.
CF (Companion)
Chaoqun Liang, Alessandro Ottaviano, Thomas Benz, Mattia Sinigaglia, Luca Benini, Angelo Garofalo, Davide Rossi
2024 J jnl
A Gigabit, DMA-enhanced Open-Source Ethernet Controller for Mixed-Criticality Systems.
CoRR
Chaoqun Liang, Alessandro Ottaviano, Thomas Benz, Mattia Sinigaglia, Luca Benini, Angelo Garofalo, Davide Rossi
2024 J jnl
A High-Performance, Energy-Efficient Modular DMA Engine Architecture.
IEEE Trans. Computers
Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel, Alessandro Ottaviano, Andreas Kurth, Torsten Hoefler, Luca Benini
2024 A conf
AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs.
DATE
Thomas Benz, Alessandro Ottaviano, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Luca Benini
2024 J jnl
CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers.
IEEE Trans. Very Large Scale Integr. Syst.
Robert Balas, Alessandro Ottaviano, Luca Benini
2024 J jnl
ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation.
Int. J. Parallel Program.
Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Antonio del Vecchio, Maicol Ciani, Davide Rossi, Luca Benini, Andrea Bartolini
2024 J jnl
ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package.
CoRR
Alessandro Ottaviano, Robert Balas, Tim Fischer, Thomas Benz, Andrea Bartolini, Luca Benini
2024 A conf
LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems Through Polling-Free and Retry-Free Operation.
DATE
Samuel Riedel, Marc Gantenbein, Alessandro Ottaviano, Torsten Hoefler, Luca Benini
2024 J jnl
LRSCwait: Enabling Scalable and Efficient Synchronization in Manycore Systems through Polling-Free and Retry-Free Operation.
CoRR
Samuel Riedel, Marc Gantenbein, Alessandro Ottaviano, Torsten Hoefler, Luca Benini
2024 J jnl
Modeling and Controlling Many-Core HPC Processors: an Alternative to PID and Moving Average Algorithms.
CoRR
Giovanni Bambini, Alessandro Ottaviano, Christian Conficoni, Andrea Tilli, Luca Benini, Andrea Bartolini
2024 A conf
PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors.
DATE
Alessandro Ottaviano, Robert Balas, Philippe Sauter, Manuel Eggimann, Luca Benini
2024 J jnl
SentryCore: A RISC-V Co-Processor System for Safe, Real-Time Control Applications.
CoRR
Michael Rogenmoser, Alessandro Ottaviano, Thomas Benz, Robert Balas, Matteo Perotti, Angelo Garofalo, Luca Benini
2024 C conf
vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-Criticality Systems.
ICCD
Enrico Zelioli, Alessandro Ottaviano, Robert Balas, Nils Wistoff, Angelo Garofalo, Luca Benini
2024 J jnl
vCLIC: Towards Fast Interrupt Handling in Virtualized RISC-V Mixed-criticality Systems.
CoRR
Enrico Zelioli, Alessandro Ottaviano, Robert Balas, Nils Wistoff, Angelo Garofalo, Luca Benini
2023 J jnl
A High-performance, Energy-efficient Modular DMA Engine Architecture.
CoRR
Thomas Benz, Michael Rogenmoser, Paul Scheffler, Samuel Riedel, Alessandro Ottaviano, Andreas Kurth, Torsten Hoefler, Luca Benini
2023 J jnl
AXI-REALM: A Lightweight and Modular Interconnect Extension for Traffic Regulation and Monitoring of Heterogeneous Real-Time SoCs.
CoRR
Thomas Benz, Alessandro Ottaviano, Robert Balas, Angelo Garofalo, Francesco Restuccia, Alessandro Biondi, Luca Benini
2023 J jnl
CV32RT: Enabling Fast Interrupt and Context Switching for RISC-V Microcontrollers.
CoRR
Robert Balas, Alessandro Ottaviano, Luca Benini
2023 J jnl
Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In.
CoRR
Alessandro Ottaviano, Thomas Benz, Paul Scheffler, Luca Benini
2023 J jnl
Cheshire: A Lightweight, Linux-Capable RISC-V Host Platform for Domain-Specific Accelerator Plug-In.
IEEE Trans. Circuits Syst. II Express Briefs
Alessandro Ottaviano, Thomas Benz, Paul Scheffler, Luca Benini
2023 J jnl
ControlPULP: A RISC-V On-Chip Parallel Power Controller for Many-Core HPC Processors with FPGA-Based Hardware-In-The-Loop Power and Thermal Emulation.
CoRR
Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Antonio del Vecchio, Maicol Ciani, Davide Rossi, Luca Benini, Andrea Bartolini
2023 J jnl
PELS: A Lightweight and Flexible Peripheral Event Linking System for Ultra-Low Power IoT Processors.
CoRR
Alessandro Ottaviano, Robert Balas, Philippe Sauter, Manuel Eggimann, Luca Benini
2023 — conf
Towards a RISC-V Open Platform for Next-generation Automotive ECUs.
MECO
Luca Cuomo, Claudio Scordino, Alessandro Ottaviano, Nils Wistoff, Robert Balas, Luca Benini, Errico Guidieri, Ida Maria Savino
2023 J jnl
Towards a RISC-V Open Platform for Next-generation Automotive ECUs.
CoRR
Luca Cuomo, Claudio Scordino, Alessandro Ottaviano, Nils Wistoff, Robert Balas, Luca Benini, Errico Guidieri, Ida Maria Savino
2023 J jnl
Yun: An Open-Source, 64-Bit RISC-V-Based Vector Processor With Multi-Precision Integer and Floating-Point Support in 65-nm CMOS.
IEEE Trans. Circuits Syst. II Express Briefs
Matteo Perotti, Matheus A. Cavalcante, Alessandro Ottaviano, Jiantao Liu, Luca Benini
2022 — conf
ControlPULP: A RISC-V Power Controller for HPC Processors with Parallel Control-Law Computation Acceleration.
SAMOS
Alessandro Ottaviano, Robert Balas, Giovanni Bambini, Corrado Bonfanti, Simone Benatti, Davide Rossi, Luca Benini, Andrea Bartolini