Alessandro Cilardo

109 papers A 16B 6C 10Misc 1Journal 50Unranked 24

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	A hardware/software architecture for multi-threaded offloading of erasure codes in distributed file systems. Future Gener. Comput. Syst. Vincenzo Maisto, Alessandro Cilardo, Emilio Billi, Chuck Fader
2026	J	`jnl`	Distilling knowledge for low-energy AIoT. J. Syst. Archit. Franca Rocco di Torrepadula, Vincenzo Maisto, Alessandro Cilardo, Nicola Mazzocca
2026	J	`jnl`	Exploring Time Predictability for High-Bandwidth Memory Technology. IEEE Trans. Emerg. Top. Comput. Alessandro Cilardo, Manuel Maddaluno
2026	J	`jnl`	The Simply-V Framework: An Extensible RISC-V Reconfigurable Soft-SoC for Open Research and Fast Prototyping. ACM Trans. Design Autom. Electr. Syst. Vincenzo Maisto, Stefano Mercogliano, Manuel Maddaluno, Alessandro Cilardo
2026	J	`jnl`	μTEE: Certification-ready RISC-V platform for secure IIoT lifecycle management. Internet Things Alessandro Cilardo, Jesús García-Rodríguez, Jose Manuel Merlos Espín, Roberto Nardone
2025	—	`conf`	A Typology of Quantum-Classical Faults. DSN-W Edoardo Giusto, Santiago Núñez-Corrales, Alessandro Cilardo, Nicola Mazzocca, Travis S. Humble
2025	—	`conf`	AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance. CF (Companion) Matteo Perotti, Vincenzo Maisto, Moritz Imfeld, Nils Wistoff, Alessandro Cilardo, Luca Benini
2025	J	`jnl`	AraOS: Analyzing the Impact of Virtual Memory Management on Vector Unit Performance. CoRR Matteo Perotti, Vincenzo Maisto, Moritz Imfeld, Nils Wistoff, Alessandro Cilardo, Luca Benini
2025	J	`jnl`	Dependable classical-quantum computing systems engineering. Frontiers Comput. Sci. Edoardo Giusto, Santiago Núñez-Corrales, Kaitlin N. Smith, Phuong Cao, Ed Younis, Paolo Rech, Flavio Vella, Betis Baheri, Alessandro Cilardo, Bartolomeo Montrucchio, Weiwen Jiang, Shuai Xu, Samudra Dasgupta, Ravishankar K. Iyer, Travis S. Humble
2025	J	`jnl`	Simply-V: A RISC-V Reconfigurable Playground Soft-SoC for Open Hardware Research and Fast Prototyping. WiPiEC Journal Vincenzo Maisto, Stefano Mercogliano, Manuel Maddaluno, Alessandro Cilardo
2025	A	`conf`	Umbra: An Efficient Framework for Trusted Execution on Modern TrustZone-Enabled Microcontrollers. DATE Stefano Mercogliano, Alessandro Cilardo
2024	J	`jnl`	An Approach to the Systematic Characterization of Multitask Accelerated CNN Inference in Edge MPSoCs. ACM Trans. Embed. Comput. Syst. Alessandro Cilardo, Vincenzo Maisto, Nicola Mazzocca, Franca Rocco di Torrepadula
2024	J	`jnl`	Dependable Classical-Quantum Computer Systems Engineering. CoRR Edoardo Giusto, Santiago Núñez-Corrales, Phuong Cao, Alessandro Cilardo, Ravishankar K. Iyer, Weiwen Jiang, Paolo Rech, Flavio Vella, Bartolomeo Montrucchio, Samudra Dasgupta, Travis S. Humble
2024	A	`conf`	Lightweight and Predictable Memory Virtualization on Medium-Size Microcontrollers. DATE Stefano Mercogliano, Daniele Ottaviano, Alessandro Cilardo, Marcello Cinque
2022	A	`conf`	A Pluggable Vector Unit for RISC-V Vector Extension. DATE Vincenzo Maisto, Alessandro Cilardo
2022	Misc	`conf`	A Proposal for FPGA-Accelerated Deep Learning Ensembles in MPSoC Platforms Applied to Malware Detection. QUATIC Alessandro Cilardo, Vincenzo Maisto, Nicola Mazzocca, Franca Rocco di Torrepadula
2022	J	`jnl`	Virtualization Over Multiprocessor Systems-on-Chip: An Enabling Paradigm for the Industrial Internet of Things. Computer Alessandro Cilardo, Marcello Cinque, Luigi De Simone, Nicola Mazzocca
2021	J	`jnl`	Evaluation of HPC Acceleration and Interconnect Technologies for High-Throughput Data Acquisition. Sensors Alessandro Cilardo
2021	C	`conf`	FPGA-based real-time monitoring support for CAN applications. DSD Alessandro Cilardo, Stefano Mercogliano
2021	—	`conf`	Memory Encryption Support for an FPGA-based RISC-V Implementation. DTIS Alessandro Cilardo
2021	J	`jnl`	Predictive Reliability and Fault Management in Exascale Systems: State of the Art and Perspectives. ACM Comput. Surv. Ramon Canal, Carles Hernández, Rafael Tornero, Alessandro Cilardo, Giuseppe Massari, Federico Reghenzani, William Fornaciari, Marina Zapater, David Atienza, Ariel Oleksiak, Wojciech Piatek, Jaume Abella
2021	J	`jnl`	SPHERE: A Multi-SoC Architecture for Next-Generation Cyber-Physical Systems Based on Heterogeneous Platforms. IEEE Access Alessandro Biondi, Daniel Casini, Giorgiomaria Cicero, Niccolò Borgioli, Giorgio C. Buttazzo, Gaetano Patti, Luca Leonardi, Lucia Lo Bello, Marco Solieri, Paolo Burgio, Ignacio Sanudo Olmedo, Angelo Ruocco, Luca Palazzi, Marko Bertogna, Alessandro Cilardo, Nicola Mazzocca, Antonino Mazzeo
2021	—	`conf`	The Italian research on HPC key technologies across EuroHPC. CF Marco Aldinucci, Giovanni Agosta, Antonio Andreini, Claudio Agostino Ardagna, Andrea Bartolini, Alessandro Cilardo, Biagio Cosenza, Marco Danelutto, Roberto Esposito, William Fornaciari, Roberto Giorgi, Davide Lengani, Raffaele Montella, Mauro Olivieri, Sergio Saponara, Daniele Simoni, Massimo Torquati
2021	J	`jnl`	The RECIPE Approach to Challenges in Deeply Heterogeneous High Performance Systems. CoRR Giovanni Agosta, William Fornaciari, David Atienza, Ramon Canal, Alessandro Cilardo, José Flich Cardo, Carles Hernández Luz, Michal Kulczewski, Giuseppe Massari, Rafael Tornero Gavilá, Marina Zapater
2021	J	`jnl`	Virtualization over Multiprocessor System-on-Chip: an Enabling Paradigm for Industrial IoT. CoRR Alessandro Cilardo, Marcello Cinque, Luigi De Simone, Nicola Mazzocca
2020	J	`jnl`	Designing a SHA-256 processor for blockchain-based IoT applications. Internet Things Raffaele Martino, Alessandro Cilardo
2020	J	`jnl`	Hardware support for thread synchronisation in an experimental manycore system. Int. J. Grid Util. Comput. Alessandro Cilardo, Mirko Gagliardi, Daniele Passaretti
2020	J	`jnl`	SHA-2 Acceleration Meeting the Needs of Emerging Applications: A Comparative Survey. IEEE Access Raffaele Martino, Alessandro Cilardo
2020	J	`jnl`	The RECIPE approach to challenges in deeply heterogeneous high performance systems. Microprocess. Microsystems Giovanni Agosta, William Fornaciari, David Atienza, Ramon Canal, Alessandro Cilardo, José Flich Cardo, Carles Hernández, Michal Kulczewski, Giuseppe Massari, Rafael Tornero Gavilá, Marina Zapater
2019	—	`conf`	A Configurable Implementation of the SHA-256 Hash Function. 3PGCIC Raffaele Martino, Alessandro Cilardo
2019	J	`jnl`	A Flexible Framework for Exploring, Evaluating, and Comparing SHA-2 Designs. IEEE Access Raffaele Martino, Alessandro Cilardo
2019	C	`conf`	Challenges in Deeply Heterogeneous High Performance Systems. DSD Giovanni Agosta, William Fornaciari, David Atienza, Ramon Canal, Alessandro Cilardo, José Flich, Carles Hernández, Michal Kulczewski, Giuseppe Massari, Rafael Tornero Gavilá, Marina Zapater
2019	A	`conf`	Lightweight hardware support for selective coherence in heterogeneous manycore accelerators. DATE Alessandro Cilardo, Mirko Gagliardi, Vincenzo Scotti
2018	J	`jnl`	An IP Core Remote Anonymous Activation Protocol. IEEE Trans. Emerg. Top. Comput. Domenico Amelino, Mario Barbareschi, Alessandro Cilardo
2018	J	`jnl`	An abstraction layer enabling pervasive hardware-reconfigurable systems. Int. J. Embed. Syst. Alessandro Cilardo, Nicola Mazzocca, Paolo Prinetto
2018	J	`jnl`	Exploring manycore architectures for next-generation HPC systems through the MANGO approach. Microprocess. Microsystems José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Edoardo Fusella, Mirko Gagliardi, Gerald Guillaume, Daniel Hofman, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Davide Zoni
2018	J	`jnl`	HtComp: bringing reconfigurable hardware to future high-performance applications. Int. J. High Perform. Comput. Netw. Alessandro Cilardo
2018	—	`conf`	Improving Deep Learning with a customizable GPU-like FPGA-based accelerator. PRIME Mirko Gagliardi, Edoardo Fusella, Alessandro Cilardo
2018	J	`jnl`	Lattice-Based Turn Model for Adaptive Routing. IEEE Trans. Parallel Distributed Syst. Edoardo Fusella, Alessandro Cilardo
2018	J	`jnl`	PowerTap: All-digital power meter modeling for run-time power monitoring. Microprocess. Microsystems Davide Zoni, Luca Cremona, Alessandro Cilardo, Mirko Gagliardi, William Fornaciari
2018	—	`ed.`	Proceedings of the 3rd International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS 2018, Manchester, United Kingdom, January 22-22, 2018 AISTECS@HiPEAC Sören Sonntag, José Manuel García Carrasco, Sébastien Rumley, Alessandro Cilardo
2018	J	`jnl`	Reducing Power Consumption of Lasers in Photonic NoCs through Application-Specific Mapping. ACM J. Emerg. Technol. Comput. Syst. Edoardo Fusella, Alessandro Cilardo
2018	—	`conf`	Reliable power and time-constraints-aware predictive management of heterogeneous exascale systems. SAMOS William Fornaciari, Giovanni Agosta, David Atienza, Carlo Brandolese, Leila Cammoun, Luca Cremona, Alessandro Cilardo, Albert Farrés, José Flich, Carles Hernández, Michal Kulchewski, Simone Libutti, José Maria Martínez, Giuseppe Massari, Ariel Oleksiak, Anna Pupykina, Federico Reghenzani, Rafael Tornero, Michele Zanella, Marina Zapater, Davide Zoni
2018	A	`conf`	Understanding turn models for adaptive routing: The modular approach. DATE Edoardo Fusella, Alessandro Cilardo
2017	—	`conf`	A Proposal for the Secure Activation and Licensing of FPGA IP Cores. ITASEC Domenico Amelino, Mario Barbareschi, Alessandro Cilardo
2017	—	`conf`	Deeply Heterogeneous Many-Accelerator Infrastructure for HPC Architecture Exploration. PARCO José Flich, Alessandro Cilardo, Mario Kovaç, Rafael Tornero, Mirko Gagliardi, Edoardo Fusella, José Maria Martínez, Tomás Picornell
2017	—	`conf`	Energy Analysis of a 4D Variational Data Assimilation Algorithm and Evaluation on ARM-Based HPC Systems. PPAM (2) Rossella Arcucci, Davide Basciano, Alessandro Cilardo, Luisa D'Amore, Filippo Mantovani
2017	J	`jnl`	H IEEE Trans. Very Large Scale Integr. Syst. Edoardo Fusella, Alessandro Cilardo
2017	C	`conf`	MANGO: Exploring Manycore Architectures for Next-GeneratiOn HPC Systems. DSD José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Etienne Cappe, Alessandro Cilardo, Leon Dragic, Alexandre Dray, Alen Duspara, William Fornaciari, Gerald Guillaume, Ynse Hoornenborg, Arman Iranfar, Mario Kovac, Simone Libutti, Bruno Maitre, José Maria Martínez, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Tomás Picornell, Igor Piljic, Anna Pupykina, Federico Reghenzani, Isabelle Staub, Rafael Tornero, Marina Zapater, Davide Zoni
2017	—	`conf`	NoC-Based Thread Synchronization in a Custom Manycore System. 3PGCIC Alessandro Cilardo, Mirko Gagliardi, Daniele Passaretti
2017	J	`jnl`	Path Setup for Hybrid NoC Architectures Exploiting Flooding and Standby. IEEE Trans. Parallel Distributed Syst. Edoardo Fusella, José Flich, Alessandro Cilardo
2017	J	`jnl`	Verification of FPGA-augmented trusted computing mechanisms based on Applied Pi Calculus. IACR Cryptol. ePrint Arch. Alessandro Cilardo, Andrea Primativo
2016	—	`conf`	A Configurable Shared Scratchpad Memory for GPU-like Processors. 3PGCIC Alessandro Cilardo, Mirko Gagliardi, Ciro Donnarumma
2016	J	`jnl`	Crosstalk-Aware Automated Mapping for Optical Networks-on-Chip. ACM Trans. Embed. Comput. Syst. Edoardo Fusella, Alessandro Cilardo
2016	J	`jnl`	Design automation for application-specific on-chip interconnects: A survey. Integr. Alessandro Cilardo, Edoardo Fusella
2016	A	`conf`	Enabling HPC for QoS-sensitive applications: The MANGO approach. DATE José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Carlo Brandolese, Alessandro Cilardo, William Fornaciari, Ynse Hoornenborg, Mario Kovac, Bruno Maitre, Giuseppe Massari, Hrvoje Mlinaric, Ermis Papastefanakis, Fabrice Roudet, Rafael Tornero, Davide Zoni
2016	J	`jnl`	Minimizing power loss in optical networks-on-chip through application-specific mapping. Microprocess. Microsystems Edoardo Fusella, Alessandro Cilardo
2016	—	`conf`	Partial FPGA bitstream encryption enabling hardware DRM in mobile environments. Conf. Computing Frontiers Mario Barbareschi, Alessandro Cilardo, Antonino Mazzeo
2016	A	`conf`	PhoNoCMap: An application mapping tool for photonic networks-on-chip. DATE Edoardo Fusella, Alessandro Cilardo
2016	A	`conf`	Securing the cloud with reconfigurable computing: An FPGA accelerator for homomorphic encryption. DATE Alessandro Cilardo, Domenico Argenziano
2015	—	`conf`	Crosstalk-Aware Mapping for Tile-Based Optical Network-on-Chip. HPCC/CSS/ICESS Edoardo Fusella, Alessandro Cilardo
2015	—	`conf`	Customizable Heterogeneous Acceleration for Tomorrow's High-Performance Computing. HPCC/CSS/ICESS Alessandro Cilardo, José Flich, Mirko Gagliardi, Rafael Tornero Gavilá
2015	J	`jnl`	Exploiting Concurrency for the Automated Synthesis of MPSoC Interconnects. ACM Trans. Embed. Comput. Syst. Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo
2015	A	`conf`	Interplay of loop unrolling and multidimensional memory partitioning in HLS. DATE Alessandro Cilardo, Luca Gallo
2015	J	`jnl`	New Techniques and Tools for Application-Dependent Testing of FPGA-Based Components. IEEE Trans. Ind. Informatics Alessandro Cilardo
2015	—	`conf`	On the Design of a Path-Setup Architecture for Exploiting Hybrid Photonic-Electronic NoCs. SiPhotonics@HiPEAC Edoardo Fusella, José Flich, Alessandro Cilardo, Antonino Mazzeo
2015	B	`conf`	Scheduling-aware interconnect synthesis for FPGA-based Multi-Processor Systems-on-Chip. FPL Edoardo Fusella, Alessandro Cilardo, Antonino Mazzeo
2015	—	`conf`	The HtComp Research Project: An Overview. 3PGCIC Alessandro Cilardo
2015	—	`conf`	The MANGO FET-HPC Project: An Overview. CSE José Flich, Giovanni Agosta, Philipp Ampletzer, David Atienza Alonso, Alessandro Cilardo, William Fornaciari, Mario Kovac, Fabrice Roudet, Davide Zoni
2015	B	`conf`	Variable-latency signed addition on FPGAs. FPL Alessandro Cilardo
2014	J	`jnl`	ASP-based optimized mapping in a simulink-to-MPSoC design flow. J. Syst. Archit. Alessandro Cilardo, Dario Socci, Nicola Mazzocca
2014	B	`conf`	Area implications of memory partitioning for high-level synthesis on FPGAs. FPL Luca Gallo, Alessandro Cilardo, David B. Thomas, Samuel Bayliss, George A. Constantinides
2014	J	`jnl`	Automated design space exploration for FPGA-based heterogeneous interconnects. Des. Autom. Embed. Syst. Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo, Nicola Mazzocca
2014	C	`conf`	Generating On-Chip Heterogeneous Systems from High-Level Parallel Code. DSD Alessandro Cilardo, Luca Gallo
2014	J	`jnl`	High Speed Speculative Multipliers Based on Speculative Carry-Save Tree. IEEE Trans. Circuits Syst. I Regul. Pap. Alessandro Cilardo, Davide De Caro, Nicola Petra, Francesco Caserta, Nicola Mazzocca, Ettore Napoli, Antonio Giuseppe Maria Strollo
2014	J	`jnl`	Improving Multibank Memory Access Parallelism with Lattice-Based Partitioning. ACM Trans. Archit. Code Optim. Alessandro Cilardo, Luca Gallo
2014	A	`conf`	Joint communication scheduling and interconnect synthesis for FPGA-based many-core systems. DATE Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo
2014	J	`jnl`	Secure distribution infrastructure for hardware digital contents. IET Comput. Digit. Tech. Alessandro Cilardo, Mario Barbareschi, Antonino Mazzeo
2013	B	`conf`	Automated synthesis of FPGA-based heterogeneous interconnect topologies. FPL Alessandro Cilardo, Edoardo Fusella, Luca Gallo, Antonino Mazzeo
2013	J	`jnl`	Design space exploration for high-level synthesis of multi-threaded applications. J. Syst. Archit. Alessandro Cilardo, Luca Gallo, Nicola Mazzocca
2013	A	`conf`	Efficient and scalable OpenMP-based system-level design. DATE Alessandro Cilardo, Luca Gallo, Antonino Mazzeo, Nicola Mazzocca
2013	J	`jnl`	Exploiting Vulnerabilities in Cryptographic Hash Functions Based on Reconfigurable Hardware. IEEE Trans. Inf. Forensics Secur. Alessandro Cilardo, Nicola Mazzocca
2013	—	`conf`	Exploring a New Dimension in Code Mobility for Ubiquitous Embedded Systems. UIC/ATC Alessandro Cilardo, Nicola Mazzocca, Paolo Prinetto
2013	J	`jnl`	Fast Parallel GF(2^m) Polynomial Multiplication for All Degrees. IEEE Trans. Computers Alessandro Cilardo
2013	—	`conf`	Heterogeneous Computing vs. Big Data: The Case of Cryptanalytical Applications. ICA3PP (2) Alessandro Cilardo
2013	—	`conf`	TrustedSIM: Towards Unified Mobile Security. UIC/ATC Alessandro Cilardo, Nicola Mazzocca, Luigi Coppolino
2011	J	`jnl`	Exploring the Potential of Threshold Logic for Cryptography-Related Operations. IEEE Trans. Computers Alessandro Cilardo
2011	B	`conf`	Revisiting Application-Dependent Test for FPGA Devices. ETS Alessandro Cilardo, Carmelo Lofiego, Antonino Mazzeo, Nicola Mazzocca
2011	A	`conf`	The potential of reconfigurable hardware for HPC cryptanalysis of SHA-1. DATE Alessandro Cilardo
2010	C	`conf`	A CellBE-based HPC Application for the Analysis of Vulnerabilities in Cryptographic Hash Functions. HPCC Alessandro Cilardo, Luigi Esposito, Antonio Veniero, Antonino Mazzeo, Vicenç Beltran, Eduard Ayguadé
2010	B	`conf`	Early Prediction of Hardware Complexity in HLL-to-HDL Translation. FPL Alessandro Cilardo, Paolo Durante, Carmelo Lofiego, Antonino Mazzeo
2009	A	`conf`	A new speculative addition architecture suitable for two's complement operations. DATE Alessandro Cilardo
2009	J	`jnl`	Efficient Bit-Parallel GF(2^m) Multiplier for a Large Class of Irreducible Pentanomials. IEEE Trans. Computers Alessandro Cilardo
2008	—	`conf`	Time Efficient Dual-Field Unit for Cryptography-Related Processing. VLSI-SoC (Selected Papers) Alessandro Cilardo, Nicola Mazzocca
2008	C	`conf`	Virtual Scan Chains for Online Testing of FPGA-based Embedded Systems. DSD Alessandro Cilardo, Nicola Mazzocca, Luigi Coppolino
2007	C	`conf`	Adaptable Parsing of Real-Time Data Streams. PDP Ferdinando Campanile, Alessandro Cilardo, Luigi Coppolino, Luigi Romano
2007	C	`conf`	Combining Programmable Hardware and Web Services Technologies for Delivering High-Performance and Interoperable Security. PDP Alessandro Cilardo, Luigi Coppolino, Antonino Mazzeo, Luigi Romano
2007	J	`jnl`	Design and implementation of a high performance architecture for providing digital time stamping services to mobile devices. Comput. Syst. Sci. Eng. Alessandro Cilardo, Domenico Cotroneo, Cristiano di Flora, Antonino Mazzeo, Luigi Romano, Stefano Russo
2007	—	`—`	Finite field arithmetic for cryptographic applications: theoretical results, algorithms, and architectures. Alessandro Cilardo
2007	C	`conf`	Performance Evaluation of Security Services: An Experimental Approach. PDP Alessandro Cilardo, Luigi Coppolino, Antonino Mazzeo, Luigi Romano
2006	J	`jnl`	Elliptic Curve Cryptography Engineering. Proc. IEEE Alessandro Cilardo, Luigi Coppolino, Nicola Mazzocca, Luigi Romano
2005	A	`conf`	A Novel Unified Architecture for Public-Key Cryptography. DATE Alessandro Cilardo, Antonino Mazzeo, Nicola Mazzocca, Luigi Romano
2005	—	`conf`	An FPGA-based Key-Store for Improving the Dependability of Security Services. WORDS Alessandro Cilardo, Antonino Mazzeo, Luigi Romano
2005	C	`conf`	High-Performance and Interoperable Security Services for Mobile Environments. HPCC Alessandro Cilardo, Luigi Coppolino, Antonino Mazzeo, Luigi Romano
2005	A	`conf`	Reconfigurable systems self-healing using mobile hardware agents. ITC Alfredo Benso, Alessandro Cilardo, Nicola Mazzocca, Liviu Miclea, Paolo Prinetto, Szilárd Enyedi
2004	J	`jnl`	A Web Services Based Architecture for Digital Time Stamping. J. Web Eng. Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese, Giuseppe Cattaneo
2004	A	`conf`	Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware. DATE Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese
2004	J	`jnl`	Exploring the design-space for FPGA-based implementation of RSA. Microprocess. Microsystems Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese
2003	—	`conf`	Using Web Services Technology for Inter-enterprise Integration of Digital Time Stamping. OTM Workshops Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese, Giuseppe Cattaneo