Albrecht P. Stroele

28 papers A 5C 3Misc 8Journal 5Unranked 7
YearRankTypeTitle / Venue / Authors
2001 — conf
Scheduling tests for low power built-in self-test.
ISCAS (5)
Tobias Schüle, Albrecht P. Stroele
2001 Misc conf
Test Scheduling for Minimal Energy Consumption under Power Constraints.
VTS
Tobias Schüle, Albrecht P. Stroele
2000 Misc conf
A Versatile BIST Technique Combining Test Registers and Accumulators.
VLSI Design
Frank Mayer, Albrecht P. Stroele
2000 J jnl
Embedded Checker Architectures for Cyclic and Low-Cost Arithmetic Codes.
J. Electron. Test.
Albrecht P. Stroele, Steffen Tarnick
2000 Misc conf
Synthesis for Arithmetic Built-In Self-Tes.
VTS
Albrecht P. Stroele
2000 C conf
Synthesizing data paths with arithmetic self-test.
ISCAS
Albrecht P. Stroele
1999 Misc conf
Programmable Embedded Self-Testing Checkers for All-Unidirectional Error-Detecting Code.
VTS
Albrecht P. Stroele, Steffen Tarnick
1999 J jnl
Signature Analysis for Test Responses of Sequential Circuits.
VLSI Design
Albrecht P. Stroele
1999 — conf
Test Scheduling with Loop Folding and Its Application to Test Configurations with Accumulators.
Asian Test Symposium
Albrecht P. Stroele, Frank Mayer
1998 Misc conf
Bit Serial Pattern Generation and Response Compaction Using Arithmetic Functions.
VTS
Albrecht P. Stroele
1998 — conf
Configuring Arithmetic Pattern Generators and Response Compactors from the RT-Modules of a Circuit.
Asian Test Symposium
Frank Mayer, Albrecht P. Stroele
1998 A conf
Embedded self-testing checkers for low-cost arithmetic codes.
ITC
Steffen Tarnick, Albrecht P. Stroele
1998 J jnl
Hardware-optimal test register insertion.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Albrecht P. Stroele, Hans-Joachim Wunderlich
1998 J jnl
Realistic Fault Modeling and Extraction of Multiple Bridging and Break Faults.
VLSI Design
Gerald Spiegel, Albrecht P. Stroele
1997 J jnl
BIST Pattern Generators Using Addition and Subtraction Operations.
J. Electron. Test.
Albrecht P. Stroele
1997 Misc conf
Methods to reduce test application time for accumulator-based self-test.
VTS
Albrecht P. Stroele, Frank Mayer
1996 C conf
Arithmetic Pattern Generators for Built-In Self-Test.
ICCD
Albrecht P. Stroele
1996 Misc conf
Test response compaction using arithmetic functions.
VTS
Albrecht P. Stroele
1995 C conf
A Self-Test Approach Using Accumulators as Test Pattern Generators.
ISCAS
Albrecht P. Stroele
1995 — conf
A unified approach to the extraction of realistic multiple bridging and break faults.
EURO-DAC
Gerald Spiegel, Albrecht P. Stroele
1995 Misc conf
Signature analysis and aliasing for sequential circuits.
VTS
Albrecht P. Stroele
1995 A conf
Test register insertion with minimum hardware cost.
ICCAD
Albrecht P. Stroele, Hans-Joachim Wunderlich
1994 A conf
Configuring Flip-Flops to BIST Registers.
ITC
Albrecht P. Stroele, Hans-Joachim Wunderlich
1994 — conf
Signature Analysis for Sequential Circuits with Reset.
EDAC-ETC-EUROASIC
Albrecht P. Stroele
1993 — conf
Partitioning and hierarchical description of self-testable designs.
VLSI
Albrecht P. Stroele
1992 A conf
Self-Test Scheduling with Bounded Test Execution.
ITC
Albrecht P. Stroele
1991 — conf
Signature Analysis and Test Scheduling for Self-Testable Circuits.
FTCS
Albrecht P. Stroele, Hans-Joachim Wunderlich
1990 A conf
Error masking in self-testable circuits.
ITC
Albrecht P. Stroele, Hans-Joachim Wunderlich