Alberto Valdes-Garcia

52 papers A 2Misc 2Journal 28Unranked 20
YearRankTypeTitle / Venue / Authors
2024 J jnl
A 24 to 30-GHz Phased Array Transceiver Front End With 2.8 to 3.1-dB RX NF and 22 to 24% TX Peak Efficiency.
IEEE J. Solid State Circuits
Wooram Lee, Caglar Ozdag, Jean-Olivier Plouchart, Alberto Valdes-Garcia, Bodhisatwa Sadhu
2024 J jnl
Eye-Beam: A mmWave 5G-Compliant Platform for Integrated Communications and Sensing Enabling AI-Based Object Recognition.
IEEE J. Sel. Areas Commun.
Arun Paidimarri, Asaf Tzadok, Sara Garcia Sanchez, Atsutse Kludze, Alexandra Gallyas-Sanhueza, Alberto Valdes-Garcia
2023 — conf
Cryogenic CMOS: design considerations for future quantum computing systems.
CICC
Rajiv V. Joshi, Jean-Olivier Plouchart, George Zettles, Scott Willenborg, Sudipto Chakraborty, Blake R. Johnson, Andrew Wack, Brian Allison, John Timmerwilke, Kevin Tien, Mark Yeck, Dereje Yilma, Alberto Valdes-Garcia, Daniel J. Friedman
2023 J jnl
Open-access millimeter-wave software-defined radios in the PAWR COSMOS testbed: Design, deployment, and experimentation.
Comput. Networks
Tingjun Chen, Prasanthi Maddala, Panagiotis Skrimponis, Jakub Kolodziejski, Abhishek Adhikari, Hang Hu, Zhihui Gao, Arun Paidimarri, Alberto Valdes-Garcia, Myung J. Lee, Sundeep Rangan, Gil Zussman, Ivan Seskar
2022 J jnl
A 24-30-GHz 256-Element Dual-Polarized 5G Phased Array Using Fast On-Chip Beam Calculators and Magnetoelectric Dipole Antennas.
IEEE J. Solid State Circuits
Bodhisatwa Sadhu, Arun Paidimarri, Duixian Liu, Mark Yeck, Caglar Ozdag, Yujiro Tojo, Wooram Lee, Kevin Xiaoxiong Gu, Jean-Olivier Plouchart, Christian W. Baks, Yusuke Uemichi, Sudipto Chakraborty, Yo Yamaguchi, Ning Guan, Alberto Valdes-Garcia
2022 — conf
A 24-to-30GHz 256-Element Dual-Polarized 5G Phased Array with Fast Beam-Switching Support for >30, 000 Beams.
ISSCC
Bodhisatwa Sadhu, Arun Paidimarri, Wooram Lee, Mark Yeck, Caglar Ozdag, Yujiro Tojo, Jean-Olivier Plouchart, Xiaoxiong Gu, Yusuke Uemichi, Sudipto Chakraborty, Yo Yamaguchi, Ning Guan, Alberto Valdes-Garcia
2022 — conf
INGR Millimeter Wave and Signal Processing Roadmap - 2022 Edition.
FNWF
Tim Lee, Harish Krishnaswamy, Paolo Gargini, Earl McCune, Harrison Chang, Anding Zhu, Alberto Valdes-Garcia
2020 J jnl
A 250-mW 60-GHz CMOS Transceiver SoC Integrated With a Four-Element AiP Providing Broad Angular Link Coverage.
IEEE J. Solid State Circuits
Bodhisatwa Sadhu, Alberto Valdes-Garcia, Jean-Olivier Plouchart, Herschel A. Ainspan, Arpit K. Gupta, Mark A. Ferriss, Mark Yeck, Mihai Sanduleanu, Xiaoxiong Gu, Christian W. Baks, Duixian Liu, Daniel J. Friedman
2020 J jnl
Multi-Mode 60-GHz Radar Transmitter SoC in 45-nm SOI CMOS.
IEEE J. Solid State Circuits
Wooram Lee, Tolga Dinc, Alberto Valdes-Garcia
2018 — conf
A 128-element Dual-Polarized Software-Defined Phased Array Radio for mm-wave 5G Experimentation.
mmNets
Bodhisatwa Sadhu, Arun Paidimarri, Mark A. Ferriss, Mark Yeck, Xiaoxiong Gu, Alberto Valdes-Garcia
2018 — conf
Antenna-in-package design and module integration for millimeter-wave communication and 5G.
VLSI-DAT
Xiaoxiong Gu, Bodhisatwa Sadhu, Duixian Liu, Christian W. Baks, Alberto Valdes-Garcia
2018 — conf
Circuit and antenna-in-package innovations for scaled mmWave 5G phased array modules.
CICC
Alberto Valdes-Garcia, Bodhisatwa Sadhu, Xiaoxiong Gu, Yahya M. Tousi, Duixian Liu, Scott K. Reynolds, Joakim Hallin, Stefan Sahl, Leonard Rexberg
2018 J jnl
Fully Integrated 94-GHz Dual-Polarized TX and RX Phased Array Chipset in SiGe BiCMOS Operating up to 105 °C.
IEEE J. Solid State Circuits
Wooram Lee, Jean-Olivier Plouchart, Caglar Ozdag, Yigit Aydogan, Mark Yeck, Alper Cabuk, Asim Kepkep, Scott K. Reynolds, Emre Apaydin, Alberto Valdes-Garcia
2018 — conf
Scaling Millimeter-Wave Phased Arrays: Challenges and Solutions.
BCICTS
Alberto Valdes-Garcia, Bodhisatwa Sadhu, Xiaoxiong Gu, Jean-Olivier Plouchart, Mark Yeck, Daniel J. Friedman
2017 — conf
7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communication.
ISSCC
Bodhisatwa Sadhu, Yahya M. Tousi, Joakim Hallin, Stefan Sahl, Scott K. Reynolds, Orjan Renstrom, Kristoffer Sjogren, Olov Haapalahti, Nadav Mazor, Bo Bokinge, Gustaf Weibull, Håkan Bengtsson, Anders Carlinger, Eric Westesson, Jan-Erik Thillberg, Leonard Rexberg, Mark Yeck, Xiaoxiong Gu, Daniel J. Friedman, Alberto Valdes-Garcia
2017 J jnl
A 28-GHz 32-Element TRX Phased-Array IC With Concurrent Dual-Polarized Operation and Orthogonal Phase and Gain Control for 5G Communications.
IEEE J. Solid State Circuits
Bodhisatwa Sadhu, Yahya M. Tousi, Joakim Hallin, Stefan Sahl, Scott K. Reynolds, Orjan Renstrom, Kristoffer Sjogren, Olov Haapalahti, Nadav Mazor, Bo Bokinge, Gustaf Weibull, Håkan Bengtsson, Anders Carlinger, Eric Westesson, Jan-Erik Thillberg, Leonard Rexberg, Mark Yeck, Xiaoxiong Gu, Mark A. Ferriss, Duixian Liu, Daniel J. Friedman, Alberto Valdes-Garcia
2015 J jnl
A 52 GHz Frequency Synthesizer Featuring a 2nd Harmonic Extraction Technique That Preserves VCO Performance.
IEEE J. Solid State Circuits
Bodhisatwa Sadhu, Mark A. Ferriss, Alberto Valdes-Garcia
2015 A conf
Co-Learning Bayesian Model Fusion: Efficient Performance Modeling of Analog and Mixed-Signal Circuits Using Side Information.
ICCAD
Fa Wang, Manzil Zaheer, Xin Li, Jean-Olivier Plouchart, Alberto Valdes-Garcia
2015 J jnl
W-band scalable phased arrays for imaging and communications.
IEEE Commun. Mag.
Xiaoxiong Gu, Alberto Valdes-Garcia, Arun Natarajan, Bodhisatwa Sadhu, Duixian Liu, Scott K. Reynolds
2014 J jnl
Adaptive Circuit Design Methodology and Test Applied to Millimeter-Wave Circuits.
IEEE Des. Test
Jean-Olivier Plouchart, Fa Wang, Xin Li, Benjamin D. Parker, Mihai A. T. Sanduleanu, Andreea Balteanu, Bodhisatwa Sadhu, Alberto Valdes-Garcia, Daniel J. Friedman
2014 J jnl
Indirect Performance Sensing for On-Chip Self-Healing of Analog and RF Circuits.
IEEE Trans. Circuits Syst. I Regul. Pap.
Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman
2013 J jnl
A 23.5 GHz PLL With an Adaptively Biased VCO in 32 nm SOI-CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap.
Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Larry T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman
2013 — conf
A 60GHz, linear, direct down-conversion mixer with mm-Wave tunability in 32nm CMOS SOI.
CICC
Mihai A. T. Sanduleanu, Alberto Valdes-Garcia, Y. Liu, Benjamin D. Parker, Shlomo Shlafman, Benny Sheinman, Danny Elad, Scott K. Reynolds, Daniel J. Friedman
2013 J jnl
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing.
IEEE J. Solid State Circuits
Bodhisatwa Sadhu, Mark A. Ferriss, Arun Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pileggi, Ramesh Harjani, José A. Tierno, Daniel J. Friedman
2013 J jnl
An Integral Path Self-Calibration Scheme for a Dual-Loop PLL.
IEEE J. Solid State Circuits
Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, José A. Tierno, Aydin Babakhani, Soner Yaldiz, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Daniel J. Friedman
2013 — conf
CMOS millimeter wave phase shifter based on tunable transmission lines.
CICC
Wayne H. Woods, Alberto Valdes-Garcia, Hanyi Ding, Jay Rascoe
2013 J jnl
Correction to "A Linearized, Low Phase Noise VCO Based 25 GHz PLL With Autonomic Biasing".
IEEE J. Solid State Circuits
Bodhisatwa Sadhu, Mark A. Ferriss, Arun S. Natarajan, Soner Yaldiz, Jean-Olivier Plouchart, Alexander V. Rylyakov, Alberto Valdes-Garcia, Benjamin D. Parker, Aydin Babakhani, Scott K. Reynolds, Xin Li, Lawrence T. Pillage, Ramesh Harjani, José A. Tierno, Daniel J. Friedman
2013 — conf
Indirect performance sensing for on-chip analog self-healing via Bayesian model fusion.
CICC
Shupeng Sun, Fa Wang, Soner Yaldiz, Xin Li, Lawrence T. Pileggi, Arun Natarajan, Mark A. Ferriss, Jean-Olivier Plouchart, Bodhisatwa Sadhu, Benjamin D. Parker, Alberto Valdes-Garcia, Mihai A. T. Sanduleanu, José A. Tierno, Daniel J. Friedman
2012 — conf
A 23.5GHz PLL with an adaptively biased VCO in 32nm SOI-CMOS.
CICC
Jean-Olivier Plouchart, Mark A. Ferriss, Arun Natarajan, Alberto Valdes-Garcia, Bodhisatwa Sadhu, Alexander V. Rylyakov, Benjamin D. Parker, Michael P. Beakes, Aydin Babakhani, Soner Yaldiz, Lawrence T. Pileggi, Ramesh Harjani, Scott K. Reynolds, José A. Tierno, Daniel J. Friedman
2012 — conf
An integral path self-calibration scheme for a 20.1-26.7GHz dual-loop PLL in 32nm SOI CMOS.
VLSIC
Mark A. Ferriss, Jean-Olivier Plouchart, Arun Natarajan, Alexander V. Rylyakov, Benjamin D. Parker, Aydin Babakhani, Soner Yaldiz, Bodhisatwa Sadhu, Alberto Valdes-Garcia, José A. Tierno, Daniel J. Friedman
2012 J jnl
Guest Editors' Introduction: Digitally Enhanced Wireless Transceivers.
IEEE Des. Test Comput.
Haralampos-G. D. Stratigopoulos, Alberto Valdes-Garcia
2012 — conf
Radio receiver techniques.
CICC
Alberto Valdes-Garcia, Ramesh Harjani
2012 — conf
Silicon-based THz circuits, systems and applications (Forum).
CICC
Alberto Valdes-Garcia
2011 J jnl
A Fully-Integrated 16-Element Phased-Array Receiver in SiGe BiCMOS for 60-GHz Communications.
IEEE J. Solid State Circuits
Arun Natarajan, Scott K. Reynolds, Ming-Da Tsai, Sean T. Nicolson, Jing-Hong Conan Zhan, Dong Gun Kam, Duixian Liu, Yen-Lin Oscar Huang, Alberto Valdes-Garcia, Brian A. Floyd
2011 J jnl
Single-element and phased-array transceiver chipsets for 60-ghz Gb/s communications.
IEEE Commun. Mag.
Alberto Valdes-Garcia, Scott K. Reynolds, Arun Natarajan, Dong Gun Kam, Duixian Liu, Jie-Wei Lai, Yen-Lin Oscar Huang, Ping-yu Chen, Ming-Da Tsai, Jing-Hong Conan Zhan, Sean Nicolson, Brian A. Floyd
2010 — conf
A 1V 17.9dBm 60GHz power amplifier in standard 65nm CMOS.
ISSCC
Jie-Wei Lai, Alberto Valdes-Garcia
2010 J jnl
A Fully Integrated 16-Element Phased-Array Transmitter in SiGe BiCMOS for 60-GHz Communications.
IEEE J. Solid State Circuits
Alberto Valdes-Garcia, Sean T. Nicolson, Jie-Wei Lai, Arun Natarajan, Ping-yu Chen, Scott K. Reynolds, Jing-Hong Conan Zhan, Dong Gun Kam, Duixian Liu, Brian A. Floyd
2010 — conf
A SiGe BiCMOS 16-element phased-array transmitter for 60GHz communications.
ISSCC
Alberto Valdes-Garcia, Sean Nicolson, Jie-Wei Lai, Arun Natarajan, Ping-yu Chen, Scott K. Reynolds, Jing-Hong Conan Zhan, Brian A. Floyd
2009 J jnl
System and Circuit Design for an MB-OFDM UWB Frequency Synthesizer.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chinmaya Mishra, Alberto Valdes-Garcia, Edgar Sánchez-Sinencio, José Silva-Martínez
2008 J jnl
A Broadband CMOS Amplitude Detector for On-Chip RF Measurements.
IEEE Trans. Instrum. Meas.
Alberto Valdes-Garcia, Radhika Venkatasubramanian, José Silva-Martínez, Edgar Sánchez-Sinencio
2008 A conf
Multi-Gbps wireless systems over 60-GHz SiGe radio link with BW-efficient noncoherent detections.
ICME
Yasunao Katayama, Daiju Nakano, Alberto Valdes-Garcia, Troy J. Beukema, Scott K. Reynolds
2007 J jnl
An 11-Band 3-10 GHz Receiver in SiGe BiCMOS for Multiband OFDM UWB Communication.
IEEE J. Solid State Circuits
Alberto Valdes-Garcia, Chinmaya Mishra, Faramarz Bahmani, José Silva-Martínez, Edgar Sánchez-Sinencio
2007 — conf
Multi-Mode Modulator and Frequency Demodulator Circuits for Gb/s Data Rate 60 GHz Wireless Transceivers.
CICC
Alberto Valdes-Garcia, Scott K. Reynolds, Troy J. Beukema
2006 J jnl
A 10-bit 44-MS/s 20-mW configurable time-interleaved pipeline ADC for a dual-mode 802.11b/Bluetooth receiver.
IEEE J. Solid State Circuits
Bo Xia, Alberto Valdes-Garcia, Edgar Sánchez-Sinencio
2006 J jnl
An Integrated Frequency Response Characterization System With a Digital Interface for Analog Testing.
IEEE J. Solid State Circuits
Alberto Valdes-Garcia, Faisal Abdel-Latif Hussien, José Silva-Martínez, Edgar Sánchez-Sinencio
2006 J jnl
Chameleon: a dual-mode 802.11b/Bluetooth receiver system design.
IEEE Trans. Circuits Syst. I Regul. Pap.
Ahmed A. Emira, Alberto Valdes-Garcia, Bo Xia, A. N. Mohieldin, Ari Yakov Valero-López, Sung Tae Moon, Chunyu Xin, Edgar Sánchez-Sinencio
2006 J jnl
On-Chip Testing Techniques for RF Wireless Transceivers.
IEEE Des. Test Comput.
Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio
2005 Misc conf
A CMOS RF RMS Detector for Built-in Testing of Wireless Transceivers.
VTS
Alberto Valdes-Garcia, Radhika Venkatasubramanian, Rangakrishnan Srinivasan, José Silva-Martínez, Edgar Sánchez-Sinencio
2005 J jnl
An On-Chip Spectrum Analyzer for Analog Built-In Testing.
J. Electron. Test.
Marcia G. Méndez-Rivera, Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio
2004 — conf
A configurable time-interleaved pipeline ADC for multi-standard wireless receivers.
ESSCIRC
Bo Xia, Alberto Valdes-Garcia, Edgar Sánchez-Sinencio
2004 Misc conf
An On-Chip Transfer Function Characterization System for Analog Built-in Testing.
VTS
Alberto Valdes-Garcia, José Silva-Martínez, Edgar Sánchez-Sinencio
2004 — conf
Frequency synthesizer for on-chip testing and automated tuning.
ISCAS (4)
Ari Yakov Valero-López, Alberto Valdes-Garcia, Edgar Sánchez-Sinencio