Alberto Ros - RankMe

126 papers A* 26A 9B 14C 8Misc 5Journal 45Unranked 19

Year	Rank	Type	Title / Venue / Authors
2026	A	`conf`	Compiler-Assisted Instruction Fusion. CGO Ravikiran Ravindranath Reddy, Sawan Singh, Arthur Perais, Alberto Ros, Alexandra Jimborean
2026	A	`conf`	Enabling Automatic Compiler-Driven Vectorization of Transformers. CGO Shreya Alladi, Alberto Ros, Alexandra Jimborean
2026	—	`conf`	ICARUS: Criticality and Reuse based Instruction Caching for Datacenter Applications. ASPLOS (2) Vedant Kalbande, Hrishikesh Jedhe Deshmukh, Alberto Ros, Biswabandan Panda
2026	J	`jnl`	Untangling the Low Accuracy of the Entangling Instruction Prefetcher. IEEE Comput. Archit. Lett. Vedant Kalbande, Biswabandan Panda, Alexandra Jimborean, Alberto Ros
2025	J	`jnl`	A Complexity-Effective Local Delta Prefetcher. IEEE Trans. Computers Agustín Navarro-Torres, Biswabandan Panda, Jesús Alastruey-Benedé, Pablo Ibáñez, Víctor Viñals Yúfera, Alberto Ros
2025	J	`jnl`	Correct Wrong Path. IEEE Comput. Archit. Lett. Bhargav Reddy Godala, Sankara Prasad Ramesh, Krishnam Tibrewala, Chrysanthos Pepi, Gino Chacon, Svilen Kanev, Gilles A. Pokam, Alberto Ros, Daniel A. Jiménez, Paul V. Gratz, David I. August
2025	A*	`conf`	Mascot: Predicting Memory Dependencies and Opportunities for Speculative Memory Bypassing. HPCA Karl H. Mose, Sebastian S. Kim, Alberto Ros, Timothy M. Jones, Robert D. Mullins
2025	A*	`conf`	No Rush in Executing Atomic Instructions. HPCA Ashkan Asgharzadeh, Josué Feliu, Manuel E. Acacio, Stefanos Kaxiras, Alberto Ros
2025	J	`jnl`	WoperTM: Got Nacks? Use Them! IEEE Comput. Archit. Lett. Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández-Pascual, Manuel E. Acacio, Alberto Ros
2024	—	`conf`	A First Exploration of Fine-Grain Coherence for Integrity Metadata. SEED Per Ekemark, Alberto Ros, Konstantinos Sagonas, Stefanos Kaxiras
2024	A*	`conf`	Alternate Path μ-op Cache Prefetching. ISCA Sawan Singh, Arthur Perais, Alexandra Jimborean, Alberto Ros
2024	—	`conf`	Bounding Speculative Execution of Atomic Regions to a Single Retry. ASPLOS (4) Eduardo José Gómez-Hernández, Juan M. Cebrian, Stefanos Kaxiras, Alberto Ros
2024	A*	`conf`	Chaining Transactions for Effective Concurrency Management in Hardware Transactional Memory. MICRO Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández-Pascual, Manuel E. Acacio, Alberto Ros
2024	A*	`conf`	Effective Context-Sensitive Memory Dependence Prediction. HPCA Sebastian S. Kim, Alberto Ros
2024	—	`conf`	Enhanced System-Level Coherence for Heterogeneous Unified Memory Architectures. IISWC Anoop Mysore Nataraja, Ricardo Fernández-Pascual, Alberto Ros
2024	J	`jnl`	Flexible Swapping for the Cloud. CoRR Milan Pandurov, Lukas Humbel, Dmitry Sepp, Adamos Ttofari, Leon Thomm, Do Le Quoc, Siddharth Chandrasekaran, Sharan Santhanam, Chuan Ye, Shai Bergman, Wei Wang, Sven Lundgren, Konstantinos Sagonas, Alberto Ros
2024	C	`conf`	Hardware Cache Locking for All Memory Updates. ICCD Ashkan Asgharzadeh, Eduardo José Gómez-Hernández, Juan M. Cebrian, Stefanos Kaxiras, Alberto Ros
2024	J	`jnl`	On the interactions between ILP and TLP with hardware transactional memory. Microprocess. Microsystems Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2024	A*	`conf`	Secure Prefetching for Secure Cache Systems. MICRO Sumon Nath, Agustín Navarro-Torres, Alberto Ros, Biswabandan Panda
2024	A*	`conf`	Temporarily Unauthorized Stores: Write First, Ask for Permission Later. MICRO Juan M. Cebrian, Magnus Jahre, Alberto Ros
2024	J	`jnl`	Wrong-Path-Aware Entangling Instruction Prefetcher. IEEE Trans. Computers Alberto Ros, Alexandra Jimborean
2023	B	`conf`	CELLO: Compiler-Assisted Efficient Load-Load Ordering in Data-Race-Free Regions. PACT Sawan Singh, Josué Feliu, Manuel E. Acacio, Alexandra Jimborean, Alberto Ros
2023	J	`jnl`	Fine-grain data classification to filter token coherence traffic. J. Parallel Distributed Comput. Bhargavi R. Upadhyay, Alberto Ros, Supriya M
2023	B	`conf`	MBPlib: Modular Branch Prediction Library. ISPASS Emilio Domínguez-Sánchez, Alberto Ros
2023	—	`conf`	Rebasing Microarchitectural Research with Industry Traces. IISWC Josué Feliu, Arthur Perais, Daniel A. Jiménez, Alberto Ros
2023	J	`jnl`	Speculative inter-thread store-to-load forwarding in SMT architectures. J. Parallel Distributed Comput. Josué Feliu, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras
2022	J	`jnl`	Analysing software prefetching opportunities in hardware transactional memory. J. Supercomput. Marina Shimchenko, J. Rubén Titos Gil, Ricardo Fernández-Pascual, Manuel E. Acacio, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean
2022	C	`conf`	Analysis of the Interactions Between ILP and TLP With Hardware Transactional Memory. PDP Víctor Nicolás-Conesa, J. Rubén Titos Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2022	A*	`conf`	Berti: an Accurate Local-Delta Data Prefetcher. MICRO Agustín Navarro-Torres, Biswabandan Panda, Jesús Alastruey-Benedé, Pablo Ibáñez, Víctor Viñals Yúfera, Alberto Ros
2022	J	`jnl`	Compiler-Assisted Compaction/Restoration of SIMD Instructions. IEEE Trans. Parallel Distributed Syst. Juan M. Cebrian, Thibaud Balem, Adrián Barredo, Marc Casas, Miquel Moretó, Alberto Ros, Alexandra Jimborean
2022	C	`conf`	Composite Instruction Prefetching. ICCD Gino Chacon, Elba Garza, Alexandra Jimborean, Alberto Ros, Paul V. Gratz, Daniel A. Jiménez, Samira Mirbagher Ajorpaz
2022	J	`jnl`	DeTraS: Delaying Stores for Friendly-Fire Mitigation in Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. J. Rubén Titos Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2022	A*	`conf`	Exploring Instruction Fusion Opportunities in General Purpose Processors. MICRO Sawan Singh, Arthur Perais, Alexandra Jimborean, Alberto Ros
2022	A*	`conf`	Free atomics: hardware atomic operations without fences. ISCA Ashkan Asgharzadeh, Juan M. Cebrian, Arthur Perais, Stefanos Kaxiras, Alberto Ros
2022	—	`conf`	Splash-4: A Modern Benchmark Suite with Lock-Free Constructs. IISWC Eduardo José Gómez-Hernández, Juan M. Cebrian, Stefanos Kaxiras, Alberto Ros
2021	A*	`conf`	A Cost-Effective Entangling Prefetcher for Instructions. ISCA Alberto Ros, Alexandra Jimborean
2021	—	`conf`	Do Not Predict - Recompute! How Value Recomputation Can Truly Boost the Performance of Invisible Speculation. SEED Christos Sakalis, Zamshed I. Chowdhury, Shayne Wadle, Ismail Akturk, Alberto Ros, Magnus Själander, Stefanos Kaxiras, Ulya R. Karpuzcu
2021	J	`jnl`	Efficient classification of private memory blocks. J. Parallel Distributed Comput. Bhargavi R. Upadhyay, Alberto Ros, Jalpa Shah
2021	A*	`conf`	Efficient, Distributed, and Non-Speculative Multi-Address Atomic Operations. MICRO Eduardo José Gómez-Hernández, Juan M. Cebrian, J. Rubén Titos Gil, Stefanos Kaxiras, Alberto Ros
2021	A*	`conf`	ITSLF: Inter-Thread Store-to-Load Forwardingin Simultaneous Multithreading. MICRO Josué Feliu, Alberto Ros, Manuel E. Acacio, Stefanos Kaxiras
2021	J	`jnl`	On Value Recomputation to Accelerate Invisible Speculation. CoRR Christos Sakalis, Zamshed I. Chowdhury, Shayne Wadle, Ismail Akturk, Alberto Ros, Magnus Själander, Stefanos Kaxiras, Ulya R. Karpuzcu
2021	B	`conf`	Splash-4: Improving Scalability with Lock-Free Constructs. ISPASS Eduardo José Gómez-Hernández, Ruixiang Shao, Christos Sakalis, Stefanos Kaxiras, Alberto Ros
2021	A*	`conf`	TSOPER: Efficient Coherence-Based Strict Persistency. HPCA Per Ekemark, Yuan Yao, Alberto Ros, Konstantinos Sagonas, Stefanos Kaxiras
2020	A*	`conf`	Boosting Store Buffer Efficiency with Store-Prefetch Bursts. MICRO Juan M. Cebrian, Stefanos Kaxiras, Alberto Ros
2020	B	`conf`	Clearing the Shadows: Recovering Lost Performance for Invisible Speculative Execution through HW/SW Co-Design. PACT Kim-Anh Tran, Christos Sakalis, Magnus Själander, Alberto Ros, Stefanos Kaxiras, Alexandra Jimborean
2020	J	`jnl`	Concurrent Irrevocability in Best-Effort Hardware Transactional Memory. IEEE Trans. Parallel Distributed Syst. J. Rubén Titos Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2020	J	`jnl`	PfTouch: Concurrent page-fault handling for Intel restricted transactional memory. J. Parallel Distributed Comput. J. Rubén Titos Gil, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2020	B	`conf`	Regional Out-of-Order Writes in Total Store Order. PACT Sawan Singh, Alexandra Jimborean, Alberto Ros
2020	A*	`conf`	Speculative Enforcement of Store Atomicity. MICRO Alberto Ros, Stefanos Kaxiras
2020	C	`conf`	TLB-based Block-Grain Classification of Private Data. PDP Bhargavi R. Upadhyay, Alberto Ros, Murty NS
2020	J	`jnl`	The Entangling Instruction Prefetcher. IEEE Comput. Archit. Lett. Alberto Ros, Alexandra Jimborean
2020	J	`jnl`	Understanding Selective Delay as a Method for Efficient Secure Speculative Execution. IEEE Trans. Computers Christos Sakalis, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean, Magnus Själander
2019	A*	`conf`	Efficient invisible speculative execution through selective delay and value prediction. ISCA Christos Sakalis, Stefanos Kaxiras, Alberto Ros, Alexandra Jimborean, Magnus Själander
2019	A*	`conf`	Filter caching for free: the untapped potential of the store-buffer. ISCA Ricardo Alves, Alberto Ros, David Black-Schaffer, Stefanos Kaxiras
2019	—	`conf`	Ghost loads: what is the cost of invisible speculation? CF Christos Sakalis, Mehdi Alipour, Alberto Ros, Alexandra Jimborean, Stefanos Kaxiras, Magnus Själander
2019	J	`jnl`	Way Combination for an Adaptive and Scalable Coherence Directory. IEEE Trans. Parallel Distributed Syst. J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández-Pascual, Alberto Ros, Salvador Petit, Julio Sahuquillo, Manuel E. Acacio
2018	J	`jnl`	Automatic Detection of Large Extended Data-Race-Free Regions with Conflict Isolation. IEEE Trans. Parallel Distributed Syst. Alexandra Jimborean, Per Ekemark, Jonatan Waern, Stefanos Kaxiras, Alberto Ros
2018	J	`jnl`	Mending Fences with Self-Invalidation and Self-Downgrade. Log. Methods Comput. Sci. Parosh Aziz Abdulla, Mohamed Faouzi Atig, Stefanos Kaxiras, Carl Leonardsson, Alberto Ros, Yunyun Zhu
2018	J	`jnl`	Non-Speculative Load Reordering in Total Store Ordering. IEEE Micro Stefanos Kaxiras, Trevor E. Carlson, Mehdi Alipour, Alberto Ros
2018	A*	`conf`	Non-Speculative Store Coalescing in Total Store Order. ISCA Alberto Ros, Stefanos Kaxiras
2018	J	`jnl`	Photonic-based express coherence notifications for many-core CMPs. J. Parallel Distributed Comput. José L. Abellán, Eduardo Padierna, Alberto Ros, Manuel E. Acacio
2018	A*	`conf`	The Superfluous Load Queue. MICRO Alberto Ros, Stefanos Kaxiras
2018	J	`jnl`	TokenTLB+CUP: A Token-Based Page Classification with Cooperative Usage Prediction. IEEE Trans. Parallel Distributed Syst. Albert Esteve, Alberto Ros, Antonio Robles, María Engracia Gómez
2017	J	`jnl`	A dedicated private-shared cache design for scalable multiprocessors. Concurr. Comput. Pract. Exp. Juan M. Cebrian, Ricardo Fernández-Pascual, Alexandra Jimborean, Manuel E. Acacio, Alberto Ros
2017	A	`conf`	Automatic detection of extended data-race-free regions. CGO Alexandra Jimborean, Jonatan Waern, Per Ekemark, Stefanos Kaxiras, Alberto Ros
2017	J	`jnl`	Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics. IEEE Trans. Parallel Distributed Syst. Alberto Ros, Carl Leonardsson, Christos Sakalis, Stefanos Kaxiras
2017	A*	`conf`	Non-Speculative Load-Load Reordering in TSO. ISCA Alberto Ros, Trevor E. Carlson, Mehdi Alipour, Stefanos Kaxiras
2017	J	`jnl`	TLB-Based Temporality-Aware Classification in CMPs with Multilevel TLBs. IEEE Trans. Parallel Distributed Syst. Albert Esteve, Alberto Ros, María Engracia Gómez, Antonio Robles, José Duato
2017	J	`jnl`	The Tag Filter Architecture: An energy-efficient cache and directory design. J. Parallel Distributed Comput. Joan J. Valls, Alberto Ros, María Engracia Gómez, Julio Sahuquillo
2017	J	`jnl`	To be silent or not: on the impact of evictions of clean data in cache-coherent multicores. J. Supercomput. Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2017	A	`conf`	Way-combining directory: an adaptive and scalable low-cost coherence directory. ICS J. Rubén Titos Gil, Antonio Flores, Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2016	Misc	`conf`	A Directory Cache with Dynamic Private-Shared Partitioning. HiPC Joan J. Valls, María Engracia Gómez, Alberto Ros, Julio Sahuquillo
2016	J	`jnl`	A Hybrid Static-Dynamic Classification for Dual-Consistency Cache Coherence. IEEE Trans. Parallel Distributed Syst. Alberto Ros, Alexandra Jimborean
2016	J	`jnl`	Are distributed sharing codes a solution to the scalability problem of coherence directories in manycores? An evaluation study. J. Supercomput. Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2016	J	`jnl`	Building Heterogeneous Unified Virtual Memories (UVMs) without the Overhead. ACM Trans. Archit. Code Optim. Konstantinos Koukos, Alberto Ros, Erik Hagersten, Stefanos Kaxiras
2016	J	`jnl`	Efficient TLB-Based Detection of Private Pages in Chip Multiprocessors. IEEE Trans. Parallel Distributed Syst. Albert Esteve, Alberto Ros, María Engracia Gómez, Antonio Robles, José Duato
2016	C	`conf`	Fencing Programs with Self-Invalidation and Self-Downgrade. FORTE Parosh Aziz Abdulla, Mohamed Faouzi Atig, Stefanos Kaxiras, Carl Leonardsson, Alberto Ros, Yunyun Zhu
2016	J	`jnl`	Mending Fences with Self-Invalidation and Self-Downgrade. CoRR Parosh Aziz Abdulla, Mohamed Faouzi Atig, Stefanos Kaxiras, Carl Leonardsson, Alberto Ros, Yunyun Zhu
2016	—	`conf`	Optimization of a Linked Cache Coherence Protocol for Scalable Manycore Coherence. ARCS Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2016	B	`conf`	POSTER: Efficient Self-Invalidation/Self-Downgrade for Critical Sections with Relaxed Semantics. PACT Alberto Ros, Carl Leonardsson, Christos Sakalis, Stefanos Kaxiras
2016	A*	`conf`	Racer: TSO consistency via race detection. MICRO Alberto Ros, Stefanos Kaxiras
2016	B	`conf`	Splash-3: A properly synchronized benchmark suite for contemporary research. ISPASS Christos Sakalis, Carl Leonardsson, Stefanos Kaxiras, Alberto Ros
2016	A	`conf`	TokenTLB: A Token-Based Page Classification Approach. ICS Albert Esteve, Alberto Ros, Antonio Robles, María Engracia Gómez, José Duato
2015	A	`conf`	A Dual-Consistency Cache Coherence Protocol. IPDPS Alberto Ros, Alexandra Jimborean
2015	J	`jnl`	Adaptive Selection of Cache Indexing Bits for Removing Conflict Misses. IEEE Trans. Computers Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García
2015	B	`conf`	An Efficient, Self-Contained, On-chip Directory: DIR1-SISD. PACT Mahdad Davari, Alberto Ros, Erik Hagersten, Stefanos Kaxiras
2015	A*	`conf`	Callback: efficient synchronization without invalidation with a directory just for spin-waiting. ISCA Alberto Ros, Stefanos Kaxiras
2015	J	`jnl`	DASC-DIR: a low-overhead coherence directory for many-core processors. J. Supercomput. Alberto Ros, Manuel E. Acacio
2015	B	`conf`	Early Experiences with Separate Caches for Private and Shared Data. e-Science Juan M. Cebrian, Alberto Ros, Ricardo Fernández-Pascual, Manuel E. Acacio
2015	—	`conf`	Fast&Furious: A Tool for Detecting Covert Racing. PARMA-DITAM@HiPEAC Alberto Ros, Stefanos Kaxiras
2015	A*	`conf`	Hierarchical private/shared classification: The key to simple and efficient coherence for clustered cache hierarchies. HPCA Alberto Ros, Mahdad Davari, Stefanos Kaxiras
2015	J	`jnl`	PS directory: a scalable multilevel directory cache for CMPs. J. Supercomput. Joan J. Valls, Alberto Ros, Julio Sahuquillo, María Engracia Gómez
2015	J	`jnl`	PS-Cache: an energy-efficient cache design for chip multiprocessors. J. Supercomput. Joan J. Valls, Alberto Ros, Julio Sahuquillo, María Engracia Gómez
2015	J	`jnl`	The Effects of Granularity and Adaptivity on Private/Shared Classification for Coherence. ACM Trans. Archit. Code Optim. Mahdad Davari, Alberto Ros, Erik Hagersten, Stefanos Kaxiras
2015	C	`conf`	The Tag Filter Cache: An Energy-Efficient Approach. PDP Joan J. Valls, Julio Sahuquillo, Alberto Ros, María Engracia Gómez
2015	A	`conf`	Turning Centralized Coherence and Distributed Critical-Section Execution on their Head: A New Approach for Scalable Distributed Shared Memory. HPDC Stefanos Kaxiras, David Klaftenegger, Magnus Norgren, Alberto Ros, Konstantinos Sagonas
2014	—	`conf`	Characterization of a List-Based Directory Cache Coherence Protocol for Manycore CMPs. Euro-Par Workshops (2) Ricardo Fernández-Pascual, Alberto Ros, Manuel E. Acacio
2013	A*	`conf`	A new perspective for efficient virtual-cache coherence. ISCA Stefanos Kaxiras, Alberto Ros
2013	—	`conf`	ECONO: Express coherence notifications for efficient cache coherency in many-core CMPs. ICSAMOS José L. Abellán, Alberto Ros, Juan Fernández Peinador, Manuel E. Acacio
2013	Misc	`conf`	Efficient Dir0B Cache Coherency for Many-Core CMPs. ICCS José L. Abellán, Alberto Ros, Juan Fernández, Manuel E. Acacio
2013	J	`jnl`	Increasing the Effectiveness of Directory Caches by Avoiding the Tracking of Noncoherent Memory Blocks. IEEE Trans. Computers Blas Cuesta, Alberto Ros, María Engracia Gómez, Antonio Robles, José Duato
2013	B	`conf`	PS-cache: An energy-efficient cache design for chip multiprocessors. PACT Joan J. Valls, Alberto Ros, Julio Sahuquillo, María Engracia Gómez
2013	B	`conf`	Temporal-Aware Mechanism to Detect Private Data in Chip Multiprocessors. ICPP Alberto Ros, Blas Cuesta, María Engracia Gómez, Antonio Robles, José Duato
2012	A	`conf`	ASCIB: adaptive selection of cache indexing bits for removing conflict misses. ISLPED Alberto Ros, Polychronis Xekalakis, Marcelo Cintra, Manuel E. Acacio, José M. García
2012	C	`conf`	Cache Miss Characterization in Hierarchical Large-Scale Cache-Coherent Systems. ISPA Alberto Ros, Blas Cuesta, María Engracia Gómez, Antonio Robles, José Duato
2012	B	`conf`	Complexity-effective multicore coherence. PACT Alberto Ros, Stefanos Kaxiras
2012	J	`jnl`	DAPSCO: Distance-aware partially shared cache organization. ACM Trans. Archit. Code Optim. Antonio García-Guirado, Ricardo Fernández-Pascual, Alberto Ros, José M. García
2012	—	`conf`	Efficient, snoopless, System-on-Chip coherence. SoCC Stefanos Kaxiras, Alberto Ros
2012	J	`jnl`	Extending Magny-Cours Cache Coherence. IEEE Trans. Computers Alberto Ros, Blas Cuesta Saez, Ricardo Fernández-Pascual, María Engracia Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato
2012	B	`conf`	PS-Dir: a scalable two-level directory cache. PACT Joan J. Valls, Alberto Ros, Julio Sahuquillo, María Engracia Gómez, José Duato
2012	C	`conf`	Using Heterogeneous Networks to Improve Energy Efficiency in Direct Coherence Protocols for Many-Core CMPs. SBAC-PAD Alberto Ros, Ricardo Fernández-Pascual, Manuel E. Acacio
2011	B	`conf`	Energy-Efficient Cache Coherence Protocols in Chip-Multiprocessors for Server Consolidation. ICPP Antonio García-Guirado, Ricardo Fernández-Pascual, Alberto Ros, José M. García
2011	A*	`conf`	Increasing the effectiveness of directory caches by deactivating coherence for private memory blocks. ISCA Blas Cuesta, Alberto Ros, María Engracia Gómez, Antonio Robles, José Duato
2011	—	`conf`	Self-related traces: An alternative to full-system simulation for NoCs. HPCS Francisco Triviño, Francisco J. Andujar, Francisco J. Alfaro, José L. Sánchez, Alberto Ros
2010	J	`jnl`	A Direct Coherence Protocol for Many-Core Chip Multiprocessors. IEEE Trans. Parallel Distributed Syst. Alberto Ros, Manuel E. Acacio, José M. García
2010	J	`jnl`	A scalable organization for distributed directories. J. Syst. Archit. Alberto Ros, Manuel E. Acacio, José M. García
2010	Misc	`conf`	EMC HiPC Alberto Ros, Blas Cuesta, Ricardo Fernández-Pascual, María Engracia Gómez, Manuel E. Acacio, Antonio Robles, José M. García, José Duato
2010	—	`conf`	Evaluation of Low-Overhead Organizations for the Directory in Future Many-Core CMPs. Euro-Par Workshops Alberto Ros, Manuel E. Acacio
2009	—	`conf`	Dealing with Traffic-Area Trade-Off in Direct Coherence Protocols for Many-Core CMPs. APPT Alberto Ros, Manuel E. Acacio, José M. García
2009	Misc	`conf`	Distance-aware round-robin mapping for large NUCA caches. HiPC Alberto Ros, Marcelo Cintra, Manuel E. Acacio, José M. García
2008	A	`conf`	DiCo-CMP: Efficient cache coherency in tiled CMP architectures. IPDPS Alberto Ros, Manuel E. Acacio, José M. García
2008	—	`conf`	Scalable Directory Organization for Tiled CMP Architectures. CDES Alberto Ros, Manuel E. Acacio, José M. García
2008	J	`jnl`	Two proposals for the inclusion of directory information in the last-level private caches of glueless shared-memory multiprocessors. J. Parallel Distributed Comput. Alberto Ros, Ricardo Fernández-Pascual, Manuel E. Acacio, José M. García
2007	Misc	`conf`	Direct Coherence: Bringing Together Performance and Scalability in Shared-Memory Multiprocessors. HiPC Alberto Ros, Manuel E. Acacio, José M. García
2006	—	`conf`	An efficient cache design for scalable glueless shared-memory multiprocessors. Conf. Computing Frontiers Alberto Ros, Manuel E. Acacio, José M. García
2005	—	`conf`	A Novel Lightweight Directory Architecture for Scalable Shared-Memory Multiprocessors. Euro-Par Alberto Ros, Manuel E. Acacio, José M. García