Alberto Nannarelli

79 papers A 5C 12Misc 6Journal 21Unranked 34

Year	Rank	Type	Title / Venue / Authors
2024	—	`conf`	Automatic Tunable Floating-Point Format Selection in a RISC-V Ecosystem. ApplePies Alberto Nannarelli, Marco Re, Gian Carlo Cardarilli, Luca Di Nunzio, Sergio Spanò
2024	J	`jnl`	Unified Digit Selection for Radix-4 Recurrence Division and Square Root. IEEE Trans. Computers David M. Harris, James E. Stine, Milos D. Ercegovac, Alberto Nannarelli, Katherine Parry, Cedar Turek
2023	J	`jnl`	An RNS-Based Initial Absolute Position Estimator for Electrical Encoders. IEEE Access Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Re, Alberto Nannarelli, Sergio Spanò
2023	Misc	`conf`	Tunable Floating Point for High Quality Audio Systems: The Sound of Numbers. ACSSC Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Riccardo La Cesa, Alberto Nannarelli, Marco Re
2022	J	`jnl`	Design Space Exploration Based Methodology for Residue Number System Digital Filters Implementation. IEEE Trans. Emerg. Top. Comput. Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Massimo Petricca, Marco Re
2022	J	`jnl`	Guest Editorial: Special Section on Emerging and Impacting Trends on Computer Arithmetic. IEEE Trans. Emerg. Top. Comput. Stuart F. Oberman, Leonel Sousa, Bogdan Pasca, Alberto Nannarelli
2021	J	`jnl`	M-PSK Demodulator With Joint Carrier and Timing Recovery. IEEE Trans. Circuits Syst. II Express Briefs Daniele Giardino, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re, Sergio Spanò
2021	J	`jnl`	Special Section on "Emerging and Impacting Trends on Computer Arithmetic". IEEE Trans. Emerg. Top. Comput. Mioara Joldes, Fabrizio Lamberti, Alberto Nannarelli
2021	J	`jnl`	Special Section on Scalable Computing for Blockchain Systems. IEEE Trans. Emerg. Top. Comput. Hong-Ning Dai Senior, Zibin Zheng, Yan Zhang, Michael Rung-Tsong Lyu, Alberto Nannarelli
2020	Misc	`conf`	FPGA Implementation of Q-RTS for Real-Time Swarm Intelligence Systems. ACSSC Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Alberto Nannarelli, Marco Re, Sergio Spanò
2020	J	`jnl`	N-Dimensional Approximation of Euclidean Distance. IEEE Trans. Circuits Syst. II Express Briefs Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re, Sergio Spanò
2020	C	`conf`	Variable Precision 16-Bit Floating-Point Vector Unit for Embedded Processors. ARITH Alberto Nannarelli
2019	J	`jnl`	A Reinforcement Learning-Based QAM/PSK Symbol Synchronizer. IEEE Access Marco Matta, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Alberto Nannarelli, Marco Re, Sergio Spanò
2019	J	`jnl`	An Efficient Hardware Implementation of Reinforcement Learning: The Q-Learning Algorithm. IEEE Access Sergio Spanò, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Daniele Giardino, Marco Matta, Alberto Nannarelli, Marco Re
2019	Misc	`conf`	Approximated Canonical Signed Digit for Error Resilient Intelligent Computation. ACSSC Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re
2019	—	`conf`	Digital Signal Processing Accelerator for RISC-V. ICECS L. Calicchia, V. Ciotoli, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re
2019	—	`conf`	Fused Multiply-Add for Variable Precision Floating-Point. SoCC Alberto Nannarelli
2019	J	`jnl`	Tunable Floating-Point Adder. IEEE Trans. Computers Alberto Nannarelli
2018	Misc	`conf`	A Power Efficient Digital Front-End for Cognitive Radio Systems. ACSSC Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re
2018	—	`conf`	Digital Architecture and ASIC Implementation of Wideband Delta DOR Spacecraft Onboard Tracker. SMACD Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Dario Gelfusa, Marco Matta, Alberto Nannarelli, Marco Re, Lorenzo Simone, Sergio Spanò
2018	—	`conf`	Tunable Floating-Point for Artificial Neural Networks. ICECS Marta Franceschi, Alberto Nannarelli, Maurizio Valle
2018	—	`conf`	Tunable Floating-Point for Embedded Machine Learning Algorithms Implementation. SMACD Marta Franceschi, Alberto Nannarelli, Maurizio Valle
2018	C	`conf`	Tunable Floating-Point for Energy Efficient Accelerators. ARITH Alberto Nannarelli
2017	—	`conf`	A multi-format floating-point multiplier for power-efficient operations. SoCC Alberto Nannarelli
2017	J	`jnl`	Improved 64-bit Radix-16 Booth Multiplier Based on Partial Product Array Height Reduction. IEEE Trans. Circuits Syst. I Regul. Pap. Elisardo Antelo, Paolo Montuschi, Alberto Nannarelli
2017	—	`conf`	Robust throughput boosting for low latency dynamic partial reconfiguration. SoCC Alberto Nannarelli, Marco Re, Gian Carlo Cardarilli, Luca Di Nunzio, M. Spaziani Brunella, Rocco Fazzolari, F. Carbonari
2016	—	`conf`	A hardware framework for on-chip FPGA acceleration. ISIC Andrea Lomuscio, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re
2016	—	`conf`	Design and simulation of a quaternary memory cell based on a physical memristor. NORCAS Jonathan Taylor, Alberto Nannarelli
2016	Misc	`conf`	Dynamically-loaded Hardware Libraries (HLL) technology for audio applications. ACSSC A. Esposito, Andrea Lomuscio, Gian Carlo Cardarilli, Luca Di Nunzio, Rocco Fazzolari, Alberto Nannarelli, Marco Re
2016	J	`jnl`	Performance/Power Space Exploration for Binary64 Division Units. IEEE Trans. Computers Alberto Nannarelli
2015	—	`conf`	A framework for dynamically-loaded hardware library (HLL) in FPGA acceleration. ISSPIT Gian Carlo Cardarilli, Leonardo Di Carlo, Alberto Nannarelli, Federico Maria Pandolfi, Marco Re
2015	—	`conf`	Characterization of RNS multiply-add units for power efficient DSP. MWSCAS Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re
2015	—	`ch.`	Power and Thermal Efficient Numerical Processing. Handbook on Data Centers Wei Liu, Alberto Nannarelli
2015	J	`jnl`	Thermal aware floorplanning incorporating temperature dependent wire delay estimation. Microprocess. Microsystems Andreas Thor Winther, Wei Liu, Alberto Nannarelli, Sarma B. K. Vrudhula
2014	C	`conf`	Decimal engine for energy-efficient multicore processors. VLSI-SoC Alberto Nannarelli
2014	—	`conf`	Energy efficient FPGA based hardware accelerators for financial applications. NORCHIP Jakob Kenn Toft, Alberto Nannarelli
2014	J	`jnl`	Guest Editors' Introduction: Special Section on Computer Arithmetic. IEEE Trans. Computers Alberto Nannarelli, Peter-Michael Seidel, Ping Tak Peter Tang
2014	—	`conf`	Twenty years of research on RNS for DSP: Lessons learned and future perspectives. ISIC Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re
2013	C	`ed.`	21st IEEE Symposium on Computer Arithmetic, ARITH 2013, Austin, TX, USA, April 7-10, 2013 IEEE Symposium on Computer Arithmetic Alberto Nannarelli, Peter-Michael Seidel, Ping Tak Peter Tang
2013	J	`jnl`	Layout-Driven Post-Placement Techniques for Temperature Reduction and Thermal Gradient Minimization. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Wei Liu, Andrea Calimera, Alberto Macii, Enrico Macii, Alberto Nannarelli, Massimo Poncino
2013	Misc	`conf`	Truncated multipliers through power-gating for degrading precision arithmetic. ACSSC Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re
2012	J	`jnl`	Comments on 'improving the speed of decimal division'. IET Comput. Digit. Tech. Tomás Lang, Alberto Nannarelli
2012	—	`conf`	Design of power efficient FPGA based hardware accelerators for financial applications. NORCHIP Jonas Stenbaek Hegner, Joakim Sindholt, Alberto Nannarelli
2012	—	`conf`	Imprecise arithmetic for low power image processing. ACSCC Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Massimo Petricca, Marco Re
2012	J	`jnl`	Power Efficient Division and Square Root Unit. IEEE Trans. Computers Wei Liu, Alberto Nannarelli
2012	—	`conf`	Power efficient design of parallel/serial FIR filters in RNS. ACSCC Massimo Petricca, Pietro Albicocco, Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re
2011	—	`conf`	FPGA Based Acceleration of Decimal Operations. ReConFig Alberto Nannarelli
2011	—	`conf`	FPGA implementation of decimal processors for hardware acceleration. NORCHIP Nicolas Borup, Jonas Dindorp, Alberto Nannarelli
2011	C	`conf`	Radix-16 Combined Division and Square Root Unit. IEEE Symposium on Computer Arithmetic Alberto Nannarelli
2011	—	`conf`	Temperature dependent wire delay estimation in floorplanning. NORCHIP Andreas Thor Winther, Wei Liu, Alberto Nannarelli, Sarma B. K. Vrudhula
2010	A	`conf`	Post-placement temperature reduction techniques. DATE Wei Liu, Alberto Nannarelli, Andrea Calimera, Enrico Macii, Massimo Poncino
2010	—	`conf`	Power dissipation challenges in multicore floating-point units. ASAP Wei Liu, Alberto Nannarelli
2009	—	`conf`	Division Unit for Binary Integer Decimals. ASAP Tomás Lang, Alberto Nannarelli
2009	—	`conf`	On-chip Thermal Modeling Based on SPICE Simulation. PATMOS Wei Liu, Andrea Calimera, Alberto Nannarelli, Enrico Macii, Massimo Poncino
2008	C	`conf`	A variant of a radix-10 combinational multiplier. ISCAS Luigi Dadda, Alberto Nannarelli
2008	C	`conf`	ADAPTO: full-adder based reconfigurable architecture for bit level operations. ISCAS Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Alberto Nannarelli
2008	—	`conf`	On the Comparison of Different Number Systems in the Implementation of Complex FIR Filters. VLSI-SoC (Selected Papers) Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re
2008	—	`conf`	Power dissipation in division. ACSCC Wei Liu, Alberto Nannarelli
2008	—	`conf`	Reducing power dissipation in pipelined accumulators. ACSCC Gian Carlo Cardarilli, Alberto Nannarelli, Marco Re
2008	—	`conf`	Session TP8b1: Computer arithmetic II. ACSCC Alberto Nannarelli
2007	J	`jnl`	A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture. IEEE Trans. Computers Tomás Lang, Alberto Nannarelli
2007	C	`conf`	Low-power adaptive filter based on RNS components. ISCAS G. L. Bernocchi, Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
2005	J	`jnl`	Digit-Recurrence Dividers with Reduced Logical Depth. IEEE Trans. Computers Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli
2005	C	`conf`	Low Latency Digit-Recurrence Reciprocal and Square-Root Reciprocal Algorithm and Architecture. IEEE Symposium on Computer Arithmetic Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli
2005	—	`conf`	Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter. ISCAS (2) Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
2004	A	`conf`	A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters. DATE Andrea Del Re, Alberto Nannarelli, Marco Re
2004	—	`conf`	Low-power implementation of polyphase filters in Quadratic Residue Number system. ISCAS (2) Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
2003	—	`conf`	Power-delay tradeoffs in residue number system. ISCAS (5) Alberto Nannarelli, Gian Carlo Cardarilli, Marco Re
2002	—	`conf`	Fast Radix-4 Retimed Division with Selection by Comparisons. ASAP Elisardo Antelo, Tomás Lang, Paolo Montuschi, Alberto Nannarelli
2002	—	`conf`	Power characterization of digital filters implemented on FPGA. ISCAS (5) Gian Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re
2001	A	`conf`	Cached-code compression for energy minimization in embedded processors. ISLPED Luca Benini, Alberto Macii, Alberto Nannarelli
2001	—	`conf`	FPGA realization of RNS to binary signed conversion architecture. ISCAS (4) Marco Re, Alberto Nannarelli, Gian Carlo Cardarilli, Roberto Lojacono
2001	—	`conf`	Tradeoffs between residue number system and traditional FIR filters. ISCAS (2) Alberto Nannarelli, Marco Re, Gian Carlo Cardarilli
1999	J	`jnl`	Low-Power Divider. IEEE Trans. Computers Alberto Nannarelli, Tomás Lang
1999	C	`conf`	Low-Power Division: Comparison among Implementations of Radix 4, 8 and 16. IEEE Symposium on Computer Arithmetic Alberto Nannarelli, Tomás Lang
1999	C	`conf`	Low-Power Radix-4 Combined Division and Square Root. ICCD Alberto Nannarelli, Tomás Lang
1998	C	`conf`	Low-power radix-8 divider. ICCD Alberto Nannarelli, Tomás Lang
1998	A	`conf`	Power-delay tradeoffs for radix-4 and radix-8 dividers. ISLPED Alberto Nannarelli, Tomás Lang
1996	A	`conf`	Low-power radix-4 divider. ISLPED Alberto Nannarelli, Tomás Lang