Alberto García Ortiz

142 papers A* 2A 10B 9C 8Misc 2Journal 42Unranked 68

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Multi-Partner Project: COIN-3D - Collaborative Innovation in 3D VLSI Reliability. CoRR George Rafael Gourdoumanis, Fotoini Oikonomou, Maria Pantazi-Kypraiou, Pavlos Stoikos, Olympia Axelou, Athanasios Tziouvaras, Georgios Karakonstantis, Tahani Aladwani, Christos Anagnostopoulos, Yixian Shen, Anuj Pathania, Alberto García Ortiz, George Floros
2025	—	`conf`	Designing Compatible Analog Circuits for Equilibrium Propagation: Implementations Using The Adjoint Method and Reciprocity Principles. ISVLSI Mohamed Watfa, Alberto García Ortiz, Gilles Sassatelli
2025	J	`jnl`	Including local feature interactions in deep non-negative matrix factorization networks improves performance. CoRR Mahbod Nouri, David Rotermund, Alberto García Ortiz, Klaus R. Pawelzik
2025	J	`jnl`	Interleaving cortex-analog mixing improves deep non-negative matrix factorization networks. Frontiers Comput. Neurosci. Mahbod Nouri, David Rotermund, Alberto García Ortiz, Klaus R. Pawelzik
2025	—	`conf`	Low-Rank Equilibrium Propagation: An Online Incremental Learning Architecture for Analog-Based Hardware Accelerators. MOCAST Mohamed Watfa, Alberto García Ortiz, Gilles Sassatelli
2025	J	`jnl`	Rescaling-Aware Training for Efficient Deployment of Deep Learning Models on Full-Integer Hardware. CoRR Lion Mueller, Alberto García Ortiz, Ardalan Najafi, Adam Fuks, Lennart Bamberg
2025	—	`conf`	Spectrum: A Holistic Evaluation Framework for Nonlinear System Modeling Methods. MOCAST Jinming Sun, Alberto García Ortiz
2025	—	`conf`	VUSA: Virtually Upscaled Systolic Array Architecture to Exploit Unstructured Sparsity in AI Acceleration. MOCAST Shereef Helal, Alberto García Ortiz, Lennart Bamberg
2025	J	`jnl`	VUSA: Virtually Upscaled Systolic Array Architecture to Exploit Unstructured Sparsity in AI Acceleration. CoRR Shereef Helal, Alberto García Ortiz, Lennart Bamberg
2024	J	`jnl`	Detailed insight into approximate circuits with error-responsive information flow tracking. it Inf. Technol. Lutz Schammer, Gianluca Martino, Amir Najafi, Alberto García Ortiz, Görschwin Fey
2024	J	`jnl`	Exploiting Neural-Network Statistics for Low-Power DNN Inference. IEEE Open J. Circuits Syst. Lennart Bamberg, Ardalan Najafi, Alberto García Ortiz
2024	A*	`conf`	GNN-assisted Back-side Clock Routing Methodology for Advance Technologies. DAC Nesara Eranna Bethur, Pruek Vanna-Iampikul, Odysseas Zografos, Lingjun Zhu, Giuliano Sisto, Dragomir Milojevic, Alberto García Ortiz, Geert Hellings, Julien Ryckaert, Francky Catthoor, Sung Kyu Lim
2024	J	`jnl`	Hier-3D: A Methodology for Physical Hierarchy Exploration of 3-D ICs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nesara Eranna Bethur, Anthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus A. Cavalcante, Samuel Riedel, Luca Benini, Sung Kyu Lim
2023	—	`conf`	Acoustic Emission Source Localization using Approximate Discrete Wavelet Transform. MOCAST Ardalan Najafi, Wanli Yu, Yarib Nevarez, Amir Najafi, Andreas Beering, Karl-Ludwig Krieger, Alberto García Ortiz
2023	—	`conf`	Approximate Computing in Critical Applications: ECG Arrhythmia Classification. MOCAST Ardalan Najafi, Amir Najafi, Julia Müller, Wanli Yu, Alberto García Ortiz
2023	J	`jnl`	CNN Sensor Analytics With Hybrid-Float6 Quantization on Low-Power Embedded FPGAs. IEEE Access Yarib Nevarez, Andreas Beering, Amir Najafi, Ardalan Najafi, Wanli Yu, Yizhi Chen, Karl-Ludwig Krieger, Alberto García Ortiz
2023	—	`conf`	Empirical Analysis of Full-System Approximation on Non-Spiking and Spiking Neural Networks. MOCAST Amir Najafi, David Rotermund, Ardalan Najafi, Klaus R. Pawelzik, Alberto García Ortiz
2023	J	`jnl`	Energy-based analog neural network framework. Frontiers Comput. Neurosci. Mohamed Watfa, Alberto García Ortiz, Gilles Sassatelli
2023	—	`conf`	Wave-Pipelined Source-Synchronous Circuit-Switched Data Transmission. MOCAST Sebastian Fischer, Amir Najafi, Alberto García Ortiz
2022	—	`conf`	DiNS: Nature Disaster in Network Simulations. MSN Nisal Hemadasa, Wanli Yu, Yanqiu Huang, Leonardo Sarmiento, Amila Wickramasinghe, Alberto García Ortiz
2022	—	`conf`	Energy-Based Analog Neural Network Framework. SOCC Mohamed Watfa, Alberto García Ortiz, Gilles Sassatelli
2022	A	`conf`	Hier-3D: A Hierarchical Physical Design Methodology for Face-to-Face-Bonded 3D ICs. ISLPED Anthony Agnesina, Moritz Brunion, Alberto García Ortiz, Francky Catthoor, Dragomir Milojevic, Manu Komalan, Matheus A. Cavalcante, Samuel Riedel, Luca Benini, Sung Kyu Lim
2021	J	`jnl`	Accelerating Spike-by-Spike Neural Networks on FPGA With Hybrid Custom Floating-Point and Logarithmic Dot-Product Approximation. IEEE Access Yarib Nevarez, David Rotermund, Klaus R. Pawelzik, Alberto García Ortiz
2021	—	`conf`	Nonlinear System Identification: Prediction Error Method vs Neural Network. MOCAST Jinming Sun, Yanqiu Huang, Wanli Yu, Alberto García Ortiz
2021	A	`conf`	Power, Performance, Area and Cost Analysis of Memory-on-Logic Face-to-Face Bonded 3D Processor Designs. ISLPED Anthony Agnesina, Moritz Brunion, Jinwoo Kim, Alberto García Ortiz, Dragomir Milojevic, Francky Catthoor, Manu Perumkunnil, Sung Kyu Lim
2020	—	`conf`	A Runtime-Reconfigurable Operand Masking Technique for Energy-Efficient Approximate Processor Architectures. MOCAST Moritz Weißbrich, Alberto García Ortiz, Guillermo Payá-Vayá
2020	—	`conf`	Accelerator Framework of Spike-By-Spike Neural Networks for Inference and Incremental Learning in Embedded Systems. MOCAST Yarib Nevarez, Alberto García Ortiz, David Rotermund, Klaus R. Pawelzik
2020	—	`conf`	Automated Toolchain for Enhanced Productivity in Reconfigurable Multi-accelerator Systems. ARC Alberto García Ortiz, Rafael Zamacola, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre
2020	A	`conf`	Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICs. DATE Lennart Bamberg, Alberto García Ortiz, Lingjun Zhu, Sai Pentapati, Da Eun Shim, Sung Kyu Lim
2020	J	`jnl`	Misalignment-aware energy modeling of narrow buses for data encoding schemes. Integr. Amir Najafi, Lennart Bamberg, Alberto García Ortiz
2020	—	`conf`	On the Effects of Data Distribution on Small-error Approximate Adders. MOCAST Yizhi Chen, Ardalan Najafi, Alberto García Ortiz
2020	—	`conf`	SATA: An Intelligent Security Aware Task Allocation for Multihop Wireless Networks. MOCAST Wanli Yu, Ojo Akinlolu, Yannik Sander, Yanqiu Huang, Alberto García Ortiz
2020	J	`jnl`	Stochastic Wave-Pipelined On-Chip Interconnect. IEEE Trans. Circuits Syst. II Express Briefs Amir Najafi, Ardalan Najafi, Alberto García Ortiz
2020	—	`conf`	Thready: A fast scheduling simulator for real-time task systems. MOCAST Robert Schmidt, Alberto García Ortiz
2019	—	`conf`	A Coding Approach to Improve the Energy Efficiency of Approximate NoCs. ReCoSoC Amir Najafi, Lennart Bamberg, Guillermo Payá Vayá, Alberto García Ortiz
2019	J	`jnl`	A Logic-on-Memory Processor-System Design With Monolithic 3-D Technology. IEEE Micro Sai Pentapati, Lingjun Zhu, Lennart Bamberg, Da Eun Shim, Alberto García Ortiz, Sung Kyu Lim
2019	J	`jnl`	Coding-Based Low-Power Through-Silicon-Via Redundancy Schemes for Heterogeneous 3-D SoCs. IEEE Trans. Very Large Scale Integr. Syst. Lennart Bamberg, Alberto García Ortiz
2019	J	`jnl`	Comparing vertical and horizontal SIMD vector processor architectures for accelerated image feature extraction. J. Syst. Archit. Moritz Weißbrich, Alberto García Ortiz, Guillermo Payá-Vayá
2019	J	`jnl`	Crosstalk optimization for through-silicon vias by exploiting temporal signal misalignment. Integr. Lennart Bamberg, Jan Moritz Joseph, Thilo Pionteck, Alberto García Ortiz
2019	J	`jnl`	DRACON: A Dedicated Hardware Infrastructure for Scalable Run-Time Management on Many-Core Systems. IEEE Access Daniel Gregorek, Jochen Rust, Alberto García Ortiz
2019	—	`conf`	Data Transfer Modeling and Optimization in Reconfigurable Multi-Accelerator Systems. ReCoSoC Alberto García Ortiz, Alfonso Rodríguez, Andrés Otero, Eduardo de la Torre
2019	J	`jnl`	EPKF: Energy Efficient Communication Schemes Based on Kalman Filter for IoT. IEEE Internet Things J. Yanqiu Huang, Wanli Yu, Enjie Ding, Alberto García Ortiz
2019	J	`jnl`	Edge effect aware low-power crosstalk avoidance technique for 3D integration. Integr. Lennart Bamberg, Amir Najafi, Alberto García Ortiz
2019	—	`ch.`	Energy-Aware Task Allocation in WSNs. Mission-Oriented Sensor Networks and Systems (1) Wanli Yu, Yanqiu Huang, Alberto García Ortiz
2019	J	`jnl`	FLINT+: A runtime-configurable emulation-based stochastic timing analysis framework. Integr. Moritz Weißbrich, Lukas Gerlach, Holger Blume, Ardalan Najafi, Alberto García Ortiz, Guillermo Payá-Vayá
2019	—	`conf`	Hardware Acceleration of Kalman Filter for Leak Detection in Water Pipeline Systems using Wireless Sensor Network. HPCS Fatma Karray, Melek Maalaoui, Abdulfattah Mohammad Obeid, Alberto García Ortiz, Mohamed Abid
2019	C	`conf`	HotAging - Impact of Power Dissipation on Hardware Degradation. ISCAS Frank Sill Torres, Alberto García Ortiz, Rolf Drechsler
2019	J	`jnl`	Integer-Value Encoding for Approximate On-Chip Communication. IEEE Access Amir Najafi, Lennart Bamberg, Ardalan Najafi, Alberto García Ortiz
2019	J	`jnl`	NoCs in Heterogeneous 3D SoCs: Co-Design of Routing Strategies and Microarchitectures. IEEE Access Jan Moritz Joseph, Lennart Bamberg, Dominik Ermel, Behnam Razi Perjikolaei, Anna Drewes, Alberto García Ortiz, Thilo Pionteck
2019	B	`conf`	Poster: Event-triggered State Estimation Meets Duty Cycling Protocol. EWSN Yanqiu Huang, Wanli Yu, Alex Leong, Alberto García Ortiz
2019	J	`jnl`	Ratatoskr: An open-source framework for in-depth power, performance and area analysis in 3D NoCs. CoRR Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar, Behnam Razi Perjikolaei, Alberto García Ortiz, Thilo Pionteck
2019	—	`conf`	Reliability of an Industrial Wireless Communication System using Approximate Units. PATMOS Mingjie Hao, Ardalan Najafi, Alberto García Ortiz, Ludwig Karsthof, Steffen Paul, Jochen Rust
2019	J	`jnl`	Simulation environment for link energy estimation in networks-on-chip with virtual channels. Integr. Jan Moritz Joseph, Lennart Bamberg, Imad Hajjar, Robert Schmidt, Thilo Pionteck, Alberto García Ortiz
2019	B	`conf`	Symbolic Circuit Analysis under an Arc Based Timing Model. ETS Görschwin Fey, Alberto García Ortiz
2019	C	`conf`	System-Level Optimization of Network-on-Chips for Heterogeneous 3D System-on-Chips. ICCD Jan Moritz Joseph, Dominik Ermel, Lennart Bamberg, Alberto García Ortiz, Thilo Pionteck
2019	J	`jnl`	System-level optimization of Network-on-Chips for heterogeneous 3D System-on-Chips. CoRR Jan Moritz Joseph, Dominik Ermel, Lennart Bamberg, Alberto García Ortiz, Thilo Pionteck
2018	J	`jnl`	A Runtime-Scalable and Hardware-Accelerated Approach to On-Board Linear Unmixing of Hyperspectral Images. Remote. Sens. Alberto García Ortiz, Alfonso Rodríguez, Raúl Guerra, Sebastián López, Andrés Otero, Roberto Sarmiento, Eduardo de la Torre
2018	J	`jnl`	A comprehensive survey on wireless sensor node hardware platforms. Comput. Networks Fatma Karray, Mohamed Wassim Jmal, Alberto García Ortiz, Mohamed Abid, Abdulfattah Mohammad Obeid
2018	A*	`conf`	Coding approach for low-power 3D interconnects. DAC Lennart Bamberg, Robert Schmidt, Alberto García Ortiz
2018	—	`conf`	Coding-aware Link Energy Estimation for 2D and 3D Networks-on-Chip with Virtual Channels. PATMOS Lennart Bamberg, Jan Moritz Joseph, Robert Schmidt, Thilo Pionteck, Alberto García Ortiz
2018	J	`jnl`	Coherent Design of Hybrid Approximate Adders: Unified Design Framework and Metrics. IEEE J. Emerg. Sel. Topics Circuits Syst. Ardalan Najafi, Moritz Weißbrich, Guillermo Payá-Vayá, Alberto García Ortiz
2018	J	`jnl`	Edge effects on the TSV array capacitances and their performance influence. Integr. Lennart Bamberg, Amir Najafi, Alberto García Ortiz
2018	—	`conf`	Exploiting Temporal Misalignment to Optimize the Interconnect Performance for 3D Integration. PATMOS Lennart Bamberg, Alberto García Ortiz
2018	—	`conf`	Joint task allocation approaches for hierarchical wireless sensor networks. MOCAST Wanli Yu, Yanqiu Huang, Enjie Ding, Alberto García Ortiz
2018	—	`conf`	Misalignment-aware delay modeling of narrow on-chip interconnects considering variability. MOCAST Amir Najafi, Lennart Bamberg, Ardalan Najafi, Alberto García Ortiz
2018	C	`conf`	Reliability Improvements for Multiprocessor Systems by Health-Aware Task Scheduling. IOLTS Robert Schmidt, Rehab Massoud, Jaan Raik, Alberto García Ortiz, Rolf Drechsler
2018	—	`conf`	Specification of Simulation Models for NoCs in Heterogeneous 3D SoCs. ReCoSoC Jan Moritz Joseph, Lennart Bamberg, Gerald Krell, Imad Hajjar, Alberto García Ortiz, Thilo Pionteck
2018	J	`jnl`	Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder. IEEE Trans. Very Large Scale Integr. Syst. Ayad Dalloo, Ardalan Najafi, Alberto García Ortiz
2018	J	`jnl`	The Agamid design-space exploration framework - Task-accurate simulation of hardware-enhanced run-time management for many-core. Des. Autom. Embed. Syst. Daniel Gregorek, Alberto García Ortiz
2017	—	`conf`	A fair comparison of adders in stochastic regime. PATMOS Ardalan Najafi, Moritz Weißbrich, Guillermo Payá Vayá, Alberto García Ortiz
2017	—	`conf`	An FPGA-based thermal emulation framework for multicore systems. PATMOS Md Shahidul Alam, Alberto García Ortiz
2017	J	`jnl`	Area and power savings via asymmetric organization of buffers in 3D-NoCs for heterogeneous 3D-SoCs. Microprocess. Microsystems Jan Moritz Joseph, Christopher Blochwitz, Alberto García Ortiz, Thilo Pionteck
2017	—	`conf`	Design method for asymmetric 3D interconnect architectures with high level models. ReCoSoC Jan Moritz Joseph, Lennart Bamberg, Sven Wrieden, Dominik Ermel, Alberto García Ortiz, Thilo Pionteck
2017	—	`conf`	Edge effect aware crosstalk avoidance technique for 3D integration. PATMOS Lennart Bamberg, Amir Najafi, Alberto García Ortiz
2017	—	`conf`	FLINT+: A runtime-configurable emulation-based stochastic timing analysis framework. PATMOS Moritz Weißbrich, Guillermo Payá-Vayá, Lukas Gerlach, Holger Blume, Ardalan Najafi, Alberto García Ortiz
2017	J	`jnl`	High-Level Energy Estimation for Submicrometric TSV Arrays. IEEE Trans. Very Large Scale Integr. Syst. Lennart Bamberg, Alberto García Ortiz
2017	J	`jnl`	Low-Power Coding: Trends and New Challenges. J. Low Power Electron. Alberto García Ortiz, Lennart Bamberg, Amir Najafi
2017	C	`conf`	Temporal redundancy latch-based architecture for soft error mitigation. IOLTS Robert Schmidt, Alberto García Ortiz, Görschwin Fey
2016	—	`conf`	A Hybrid Algorithm to Conservatively Check the Robustness of Circuits. ISVLSI Niels Thole, Görschwin Fey, Alberto García Ortiz
2016	—	`conf`	A programmable and reconfigurable core for binary image processing. ReCoSoC Ayad Dalloo, Alberto García Ortiz
2016	—	`conf`	A simulation environment for design space exploration for asymmetric 3D-Network-on-Chip. ReCoSoC Jan Moritz Joseph, Sven Wrieden, Christopher Blochwitz, Alberto García Ortiz, Thilo Pionteck
2016	J	`jnl`	Analysis of PKF: A Communication Cost Reduction Scheme for Wireless Sensor Networks. IEEE Trans. Wirel. Commun. Yanqiu Huang, Wanli Yu, Christof Osewold, Alberto García Ortiz
2016	B	`conf`	EARNPIPE: A Testbed for Smart Water Pipeline Monitoring Using Wireless Sensor Network. KES Fatma Karray, Alberto García Ortiz, Mohamed Wassim Jmal, Abdulfattah Mohammad Obeid, Mohamed Abid
2016	—	`conf`	ERRCA: A buffer-efficient reconfigurable optical Network-on-Chip with permanent-error recognition. ReCoSoC Wolfgang Büter, Dominic Oehlert, Alberto García Ortiz
2016	—	`conf`	Energy modeling of coupled interconnects including intrinsic misalignment effects. PATMOS Amir Najafi, Lennart Bamberg, Ardalan Najafi, Alberto García Ortiz
2016	B	`conf`	Modeling Optimal Dynamic Scheduling for Energy-Aware Workload Distribution in Wireless Sensor Networks. DCOSS Wanli Yu, Yanqiu Huang, Alberto García Ortiz
2016	B	`conf`	PKF-ST: A Communication Cost Reduction Scheme Using Spatial and Temporal Correlation for Wireless Sensor Networks. EWSN Yanqiu Huang, Wanli Yu, Alberto García Ortiz
2016	—	`conf`	Run-time schedulability check of real-time tasks for energy efficiency. PATMOS Parham Haririan, Alberto García Ortiz
2016	A	`conf`	Synthesis of approximate coders for on-chip interconnects using reversible logic. DATE Robert Wille, Oliver Keszöcze, Stefan Hillmich, Marcel Walter, Alberto García Ortiz
2015	—	`conf`	A decentralised, autonomous, and congestion-aware thermal monitoring infrastructure for photonic network-on-chip. ReCoSoC Wolfgang Büter, Yanqiu Huang, Daniel Gregorek, Alberto García Ortiz
2015	—	`conf`	A framework for hardware-based DVFS management in multicore mixed-criticality systems. ReCoSoC Parham Haririan, Alberto García Ortiz
2015	B	`conf`	A rapid prototyping framework for nano-photonic accelerators. FPL Wolfgang Büter, Alberto García Ortiz, A. Ali, S. Mahmood, S. Arefin, V. V. Parsi Sreenivas, R. B. Bergman
2015	B	`conf`	An altruistic compression-scheduling scheme for cluster-based wireless sensor networks. SECON Wanli Yu, Yanqiu Huang, Alberto García Ortiz
2015	—	`conf`	Area and power savings via buffer reorganization in asymmetric 3D-NoCs for heterogeneous 3D-SoCs. NORCAS Jan Moritz Joseph, Christopher Blochwitz, Thilo Pionteck, Alberto García Ortiz
2015	—	`conf`	Conservatively Analyzing Transient Faults. ISVLSI Niels Thole, Görschwin Fey, Alberto García Ortiz
2015	—	`conf`	Message from the chairs. ReCoSoC Alberto García Ortiz, Daniel Gregorek, Eduardo de la Torre, Juha Plosila
2015	—	`conf`	Predictable photonic interconnects using an autonomous channel management and a TDMA-NoC. ReCoSoC Wolfgang Büter, Christof Osewold, Awais Ahmed, Daniel Gregorek, Alberto García Ortiz
2015	J	`jnl`	Proceedings of the Workshop on High Performance Energy Efficient Embedded Systems (HIP3ES) 2015. CoRR Francisco Corbera, Andrés Rodríguez, Rafael Asenjo, Angeles G. Navarro, Antonio Vilches, María Jesús Garzarán, Ismat Chaib Draa, Jamel Tayeb, Smaïl Niar, Mikael Desertot, Daniel Gregorek, Robert Schmidt, Alberto García Ortiz, Pedro López-García, Rémy Haemmerlé, Maximiliano Klemen, Umer Liqat, Manuel V. Hermenegildo, Radim Vavrík, Albert Saà-Garriga, David Castells-Rufas, Jordi Carrabina
2015	—	`conf`	The DRACON Embedded Many-Core: Hardware-Enhanced Run-Time Management Using a Network of Dedicated Control Nodes. ISVLSI Daniel Gregorek, Alberto García Ortiz
2015	J	`jnl`	Transaction Level Analysis for a Clustered and Hardware-Enhanced Task Manager on Homogeneous Many-Core Systems. CoRR Daniel Gregorek, Robert Schmidt, Alberto García Ortiz
2014	—	`conf`	A coding-based configurable and asymmetrical redundancy scheme for 3-D interconnects. ReCoSoC Christof Osewold, Wolfgang Büter, Alberto García Ortiz
2014	—	`conf`	A transaction-level framework for design-space exploration of hardware-enhanced operating systems. ISSoC Daniel Gregorek, Alberto García Ortiz
2014	J	`jnl`	Accurate Energy-Aware Workload Distribution for Wireless Sensor Networks Using a Detailed Communication Energy Cost Model. J. Low Power Electron. Yanqiu Huang, Wanli Yu, Alberto García Ortiz
2014	A	`conf`	DCM: An IP for the autonomous control of optical and electrical reconfigurable NoCs. DATE Wolfgang Büter, Christof Osewold, Daniel Gregorek, Alberto García Ortiz
2014	—	`conf`	Non-intrusive DVFS emulation in gem5 with application to self-aware architectures. ReCoSoC Parham Haririan, Alberto García Ortiz
2013	C	`conf`	A Scalable Hardware Implementation of a Best-Effort Scheduler for Multicore Processors. DSD Daniel Gregorek, Christof Osewold, Alberto García Ortiz
2013	—	`conf`	A review on wireless sensor network for water pipeline monitoring applications. CTS Mohammed S. BenSaleh, Syed Manzoor Qasim, Abdulfattah Mohammad Obeid, Alberto García Ortiz
2013	Misc	`conf`	An optimisation algorithm for minimising energy dissipation in NoC-based hard real-time embedded systems. RTNS M. Norazizi Sham Mohd Sayuti, Leandro Soares Indrusiak, Alberto García Ortiz
2013	—	`conf`	PKF: A communication cost reduction schema based on Kalman filter and data prediction for Wireless Sensor Networks. SoCC Yanqiu Huang, Wanli Yu, Alberto García Ortiz
2012	A	`conf`	Automatic design of low-power encoders using reversible circuit synthesis. DATE Robert Wille, Rolf Drechsler, Christof Osewold, Alberto García Ortiz
2010	—	`conf`	Practical and Theoretical Considerations on Low-Power Probability-Codes for Networks-on-Chip. PATMOS Alberto García Ortiz, Leandro Soares Indrusiak
2009	J	`jnl`	Low-Power Coding for Networks-on-Chip with Virtual Channels. J. Low Power Electron. Alberto García Ortiz, Leandro Soares Indrusiak, Tudor Murgan, Manfred Glesner
2008	—	`conf`	A novel leakage-estimation method for input-vector control. APCCAS Hans-Peter Keil, Massoud Momeni, Andre Guntoro, Alberto García Ortiz, Manfred Glesner
2008	—	`conf`	PMD: A Low-Power Code for Networks-on-Chip Based on Virtual Channels. PATMOS Alberto García Ortiz, Leandro Soares Indrusiak, Tudor Murgan, Manfred Glesner
2007	—	`conf`	Inserting Data Encoding Techniques into NoC-Based Systems. ISVLSI José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis
2007	—	`conf`	On the Necessity of Combining Coding with Spacing and Shielding for Improving Performance and Power in Very Deep Sub-micron Interconnects. PATMOS Tudor Murgan, Petru Bogdan Bacinschi, Sujan Pandey, Alberto García Ortiz, Manfred Glesner
2007	J	`jnl`	Signal Activity Analysis for High-Level Power Estimation in Time-Shared Linear Systems. J. Low Power Electron. Alberto García Ortiz, Tudor Murgan, Manfred Glesner
2006	A	`conf`	A high-level compact pattern-dependent delay model for high-speed point-to-point interconnects. ICCAD Tudor Murgan, Massoud Momeni, Alberto García Ortiz, Manfred Glesner
2006	—	`conf`	Adaptive Coding in Networks-on-Chip: Transition Activity Reduction Versus Power Overhead of the Codec Circuitry. PATMOS José Carlos S. Palma, Leandro Soares Indrusiak, Fernando Gehm Moraes, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis
2006	—	`conf`	Evaluating the Impact of Data Encoding Techniques on the Power Consumption in Networks-on-Chip. ISVLSI José Carlos S. Palma, Ricardo A. L. Reis, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Fernando Gehm Moraes
2006	—	`conf`	Partial Bus-Invert Bus Encoding Schemes for Low-Power DSP Systems Considering Inter-wire Capacitance. PATMOS Tudor Murgan, Petru Bogdan Bacinschi, Alberto García Ortiz, Manfred Glesner
2005	—	`conf`	A linear model for high-level delay estimation in VDSM on-chip interconnects. ISCAS (2) Alberto García Ortiz, Tudor Murgan, Mihail Petrov, Manfred Glesner
2004	—	`conf`	Accurate capture of timing parameters in inductively-coupled on-chip interconnects. SBCCI Tudor Murgan, Clemens Schlachta, Mihail Petrov, Leandro Soares Indrusiak, Alberto García Ortiz, Manfred Glesner, Ricardo A. L. Reis
2004	—	`conf`	Moment-Based Estimation of Switching Activity for Correlated Distributions. PATMOS Alberto García Ortiz, Tudor Murgan, Manfred Glesner
2004	—	`conf`	On Timing and Power Consumption in Inductively Coupled On-Chip Interconnects. PATMOS Tudor Murgan, Alberto García Ortiz, Clemens Schlachta, Heiko Zimmer, Mihail Petrov, Manfred Glesner
2003	—	`conf`	A multi-path high speed Viterbi decoder. ICECS Abdulfattah Mohammad Obeid, Alberto García Ortiz, Mihail Petrov, Manfred Glesner
2003	—	`conf`	Arbitrary function approximation in HDLs with application to the N-body problem. FPT Chun Hok Ho, Kuen Hung Tsoi, Jackson H. C. Yeung, Yuet Ming Lam, Kin-Hong Lee, Philip Heng Wai Leong, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner
2003	C	`conf`	Emulation of Analog Components for the Rapid Prototyping of Wireless Baseband Systems. IEEE International Workshop on Rapid System Prototyping Ralf Ludewig, Alberto García Ortiz, Tudor Murgan, Juan Jesús Ocampo Hidalgo, Manfred Glesner
2003	B	`conf`	Evaluation and Run-Time Optimization of On-chip Communication Structures in Reconfigurable Architectures. FPL Tudor Murgan, Mihail Petrov, Alberto García Ortiz, Ralf Ludewig, Peter Zipf, Thomas Hollstein, Manfred Glesner, Bernard Ölkrug, Jörg Brakensiek
2003	J	`jnl`	Hardware-Assisted Signal Activity Analysis for Power Estimation in Rapid Prototyped Systems. Des. Autom. Embed. Syst. Ralf Ludewig, Alberto García Ortiz, Tudor Murgan, Manfred Glesner
2003	A	`conf`	Moment-Based Power Estimation in Very Deep Submicron Technologies. ICCAD Alberto García Ortiz, Lukusa D. Kabulepa, Tudor Murgan, Manfred Glesner
2003	—	`conf`	Switching Activity Estimation in Non-linear Architectures. PATMOS Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner
2003	Misc	`conf`	Transition Activity Estimation for General Correlated Data Distributions. VLSI Design Alberto García Ortiz, Tudor Murgan, Manfred Glesner
2002	—	`conf`	Analysis of bandpass sigma-delta modulator architectures. ICECS Juan Jesús Ocampo Hidalgo, Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner
2002	—	`conf`	Design of an efficient OFDM burst synchronization scheme. ISCAS (3) Lukusa D. Kabulepa, Alberto García Ortiz, Manfred Glesner
2002	A	`conf`	Efficient estimation of signal transition activity in MAC architectures. ISLPED Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner
2002	A	`conf`	Estimation of Power Consumption in Encoded Data Buses. DATE Alberto García Ortiz, Lukusa D. Kabulepa, Manfred Glesner
2002	B	`conf`	Fly - A Modifiable Hardware Compiler. FPL Chun Hok Ho, Philip Heng Wai Leong, Kuen Hung Tsoi, Ralf Ludewig, Peter Zipf, Alberto García Ortiz, Manfred Glesner
2002	—	`conf`	Power Consumption in Point-to-Point Interconnect Architectures. SBCCI Alberto García Ortiz, Tudor Murgan, Leandro Soares Indrusiak, Manfred Glesner
2002	C	`conf`	Power Estimation Based on Transition Activity Analysis with an Architecture Precise Rapid Prototyping System. IEEE International Workshop on Rapid System Prototyping Ralf Ludewig, Alberto García Ortiz, Tudor Murgan, Manfred Glesner
2002	—	`conf`	Power reduction techniques for an OFDM burst synchronization core. ISCAS (1) Lukusa D. Kabulepa, Alberto García Ortiz, Manfred Glesner
2002	C	`conf`	Prototyping of a High Performance Generic Viterbi Decoder. IEEE International Workshop on Rapid System Prototyping Abdulfattah Mohammad Obeid, Alberto García Ortiz, Ralf Ludewig, Manfred Glesner