Alberto Bosio - RankMe

274 papers A* 1A 26B 22C 56Misc 14Journal 62Unranked 90

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Benchmark Suite for Resilience Assessment of Deep Learning Models. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cristiana Bolchini, Alberto Bosio, Luca Cassano, Antonio Miele, Salvatore Pappalardo, Dario Passarello, Annachiara Ruospo, Ernesto Sánchez, Matteo Sonza Reorda, Vittorio Turco
2026	—	`conf`	Case Study: Improving the Robustness of Photonic Neural Networks Against Memory Faults. LATS Mauricio Gomes de Queiroz, Leonardo Alexandrino De Melo, Mateus Vidaletti Costa, Salvatore Pappalardo, Fabio Pavanello, Ian O'Connor, Alberto Bosio
2026	J	`jnl`	Exploiting Modular Redundancy for approximating Random Forest classifiers. Future Gener. Comput. Syst. Antonio Emmanuele, Mario Barbareschi, Alberto Bosio
2026	—	`conf`	M-EL2N: Data-Efficient Fault Injection Through Sample Difficulty Analysis. LATS Nicolò Bellarmino, Alberto Bosio, Ahmed Al Kaf, Mounir Benabdenbi, Régis Leveugle, Riccardo Cantoro
2026	J	`jnl`	OpRA: Optimizing Resiliency Assessment for Deep Neural Networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Nicolò Bellarmino, Salvatore Barone, Salvatore Pappalardo, Alberto Bosio, Riccardo Cantoro
2026	J	`jnl`	Reliability analysis of hardware accelerators for decision tree-based classifier systems. Future Gener. Comput. Syst. Mario Barbareschi, Salvatore Barone, Alberto Bosio, Antonio Emmanuele
2026	—	`conf`	Spectral Vs. Spatial Pruning: Fault Resilience Analysis for Extremely Sparse DNNs. LATS Manar Gani, Leonardo Alexandrino De Melo, Alberto Bosio, Rodrigo Possamai Bastos, David Novo
2025	A	`conf`	A Benchmark Suite to Evaluate DNN's Resilience. ITC Cristiana Bolchini, Alberto Bosio, Luca Cassano, Antonio Miele, Salvatore Pappalardo, Dario Passariello, Annachiara Ruospo, Ernesto Sánchez, Matteo Sonza Reorda, Vittorio Turco
2025	J	`jnl`	A Genetic Approach for Automatic AxC Design Exploration at RTL Based on Assertion Mining and Fault Analysis. IEEE Trans. Emerg. Top. Comput. Alberto Bosio, Samuele Germiniani, Graziano Pravadelli, Marcello Traiola
2025	J	`jnl`	A Growing and Thriving Electronic Design, Automation, and Test Community: A DATE 2025 Perspective. IEEE Des. Test Aida Todri-Sanial, Theocharis Theocharides, Valeria Bertacco, Alberto Bosio
2025	J	`jnl`	Accelerating LWE-Based Post-Quantum Cryptography with Approximate Computing. IACR Cryptol. ePrint Arch. Diamante Simone Crescenzo, Emanuele Valea, Alberto Bosio
2025	C	`conf`	Automatic generation of input-aware approximate arithmetic circuits. DDECS Mario Barbareschi, Salvatore Barone, Alberto Bosio, Bastien Deveautour, Ali Piri, Marcello Traiola
2025	—	`conf`	AxEnMULT: Design of an Efficient and Reliable Approximate Encoding-Based Multiplier. ISVLSI Ahsan Rafiq, Alberto Bosio, Salvatore Pappalardo, Maksim Jenihhin
2025	C	`conf`	DEAR-CNN: Data-Efficient Assessment of Resiliency in Convolutional Neural Networks. DDECS Nicolò Bellarmino, Alberto Bosio, Riccardo Cantoro, Annachiara Ruospo, Ernesto Sánchez
2025	B	`conf`	European Test Symposium Teams: an Anniversary Snapshot. ETS Maksim Jenihhin, Jaan Raik, Artur Jutman, Natalia Cherezova, Raimund Ubar, Liviu Miclea, Szilárd Enyedi, I. Stefan, Ovidiu Stan, Cosmina Corches, Z. Peng, Petru Eles, Rolf Drechsler, S. Eggersglüß, Görschwin Fey, Andreas Glowatz, Daniel Tille, Georges G. E. Gielen, Anthony Coyette, Wim Dobbelaere, Ronny Vanhooren, P.-Y. Chuang, Erik Jan Marinissen, Giorgio Di Natale, M. Barragan, Paolo Maistri, S. Mir, Vatajelu I. Vatajelu, Paolo Bernardi, S. Di Carlo, Paolo Prinetto, Matteo Sonza Reorda, Massimo Violante, Haralampos-G. Stratigopoulos, M. K. Michael, Stelios Neophytou, Stavros Hadjitheophanous, Kyriakos Christou, M. Skitsas, Alberto Bosio, Bastien Deveautour, P. Girard, Marcello Traiola, Arnaud Virazel, F. Fernandes Dos Santos, Angeliki Kritikakou, Gioele Casagranda, Marzio Vallero, Flavio Vella, Paolo Rech, Letícia Maria Bolzani Poehls, Milos Krstic, Marko S. Andjelkovic, F. Vargas, Grigor Tshagharyan, Gurgen Harutyunyan, Valery A. Vardanian, Samvel K. Shoukourian, Yervant Zorian, Jennifer Dworak, Kundan Nepal, Theodore W. Manikas, Mottaqiallah Taouil, Moritz Fieback, Anteneh Gebregiorgis, Rajendra Bishnoi, Said Hamdioui, Abhijit Chatterjee, A. Saha, Suhasini Komarraju, K. Ma, Chandramouli N. Amarnath, Mehdi Baradaran Tahoori, Mahta Mayahinia, Maryam Rajabalipanah, Katayoon Basharkhah, N. Nosrati, Zahra Jahanpeima, Zain Navabi, Hans-Joachim Wunderlich, Sybille Hellebrand
2025	Misc	`conf`	MicroFI: TensorFlow Lite based Fault Injection Framework for Microcontrollers. VTS Leonardo Alexandrino De Melo, Rodrigo Possamai Bastos, Alberto Bosio
2025	C	`conf`	Non-Volatile Ferroelectric-AND (FeAND) Memory Cell Design. VLSI-SoC Basile Darne, Miqueas Filsinger, Alberto Bosio, Damien Deleruyelle, Ian O'Connor, Bertrand Vilquin, Cédric Marchand
2025	J	`jnl`	Reliability of Deep Neural Networks: Impact and Open Issues. IEEE Des. Test Annachiara Ruospo, Salvatore Pappalardo, Vittorio Turco, Alberto Bosio, Ernesto Sánchez
2025	J	`jnl`	SAFFIRA A Framework for Assessing the Reliability of Systolic-Array DNN Accelerators. J. Circuits Syst. Comput. Salvatore Pappalardo, Nicolò Bellarmino, Bastien Deveautour, Alberto Bosio, Mahdi Taheri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin
2025	—	`conf`	Special Session Paper: FeMFET-Based High Performance, Ultra-Low Power Memory Cells for Reliable State Retention of Dataflow Networks. DFT Basile Darne, Abrarul Karim, Paul-Antoine Matrangolo, Joachim Falk, Ian O'Connor, Cédric Marchand, Alberto Bosio, Jürgen Teich
2025	Misc	`conf`	Special Session: Trustworthy Hardware-AI at the Cloud. VTS Francesco Angione, Paolo Bernardi, Alberto Bosio, Harish Dattatraya Dixit, Salvatore Pappalardo, Annachiara Ruospo, Ernesto Sánchez, Arani Sinha, Vittorio Turco
2024	C	`conf`	3D VNWFET-Based Standard Cell Library Design Flow: from Circuit and Physical Design to Logic Synthesis. VLSI-SoC Sara Mannaa, Cédric Marchand, Damien Deleruyelle, Bastien Deveautour, Alberto Bosio, Christoph Lenz, Oskar Baumgartner, Ian O'Connor
2024	B	`conf`	Approximate Fault-Tolerant Neural Network Systems. ETS Marcello Traiola, Salvatore Pappalardo, Ali Piri, Annachiara Ruospo, Bastien Deveautour, Ernesto Sánchez, Alberto Bosio, Sepide Saeedi, Alessio Carpegna, Anil Bayram Gogebakan, Enrico Magliano, Alessandro Savino
2024	A	`conf`	FVLLMONTI: The 3D Neural Network Compute Cube $(N^{2}C^{2})$ Concept for Efficient Transformer Architectures Towards Speech-to-Speech Translation. DATE Ian O'Connor, Sara Mannaa, Alberto Bosio, Bastien Deveautour, Damien Deleruyelle, Tetiana Obukhova, Cédric Marchand, Jens Trommer, Çigdem Çakirlar, Bruno Neckel Wesling, Thomas Mikolajick, Oskar Baumgartner, Mischa Thesberg, David Pirker, Christoph Lenz, Zlatan Stanojevic, Markus Karner, Guilhem Larrieu, Sylvain Pelloquin, Konstantinous Moustakas, Jonas Müller, Giovanni Ansaloni, Alireza Amirshahi, David Atienza, Jean-Luc Rouas, Leila Ben Letaifa, Georgeta Bordeall, Charles Brazier, Chhandak Mukherjee, Marina Deng, Yifan Wang, Marc François, Houssem Rezgui, Reveil Lucas, Cristell Maneux
2024	J	`jnl`	Guest Editorial IEEE Transactions on Emerging Topics in Special Section on Emerging In-Memory Computing Architectures and Applications. IEEE Trans. Emerg. Top. Comput. Alberto Bosio, Ronald F. DeMara, Deliang Fan, Nima Taherinejad
2024	C	`conf`	Hardware Accelerator for FIPS 202 Hash Functions in Post-Quantum Ready SoCs. IOLTS Diamante Simone Crescenzo, Rafael Carrera Rodriguez, Riccardo Alidori, Florent Bruguier, Emanuele Valea, Pascal Benoit, Alberto Bosio
2024	C	`conf`	Heterogeneous Approximation of DNN HW Accelerators based on Channels Vulnerability. VLSI-SoC Natalia Cherezova, Salvatore Pappalardo, Mahdi Taheri, Mohammad Hasan Ahmadilivani, Bastien Deveautour, Alberto Bosio, Jaan Raik, Maksim Jenihhin
2024	A	`conf`	High-Performance Data Mapping for BNNs on PCM-Based Integrated Photonics. DATE Taha Shahroodi, Raphael Cardoso, Stephan Wong, Alberto Bosio, Ian O'Connor, Said Hamdioui
2024	J	`jnl`	High-Performance Data Mapping for BNNs on PCM-based Integrated Photonics. CoRR Taha Shahroodi, Raphael Cardoso, Stephan Wong, Alberto Bosio, Ian O'Connor, Said Hamdioui
2024	—	`conf`	How Systolic Array Dataflow impacts on the resilience to hardware faults. DTTIS Salvatore Pappalardo, Bastien Deveautour, Alberto Bosio
2024	—	`conf`	Investigating on Gradient Regularization for Testing Neural Networks. LOD (2) Nicolò Bellarmino, Alberto Bosio, Riccardo Cantoro, Annachiara Ruospo, Ernesto Sánchez, Giovanni Squillero
2024	—	`conf`	Reliable and Efficient hardware for Trustworthy Deep Neural Networks. DTTIS Salvatore Pappalardo, Ali Piri, Annachiara Ruospo, Bastien Deveautour, Ernesto Sánchez, Alberto Bosio
2024	A	`conf`	Resilience of Deep Learning Applications: Where We are and Where We Want to Go. DATE Cristiana Bolchini, Alberto Bosio
2024	—	`conf`	Resiliency Approaches in Convolutional, Photonic, and Spiking Neural Networks. LATS Alberto Bosio, M. Gomes, Fabio Pavanello, A. Porsia, Annachiara Ruospo, Ernesto Sánchez, Elena I. Vatajelu
2024	C	`conf`	Robustness of Redundancy-Hardened Convolutional Neural Networks Against Adversarial Attacks. PRDC Leonardo Alexandrino De Melo, Mauricio Gomes de Queiroz, Alberto Bosio, Rodrigo Possamai Bastos
2024	C	`conf`	SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators. DDECS Mahdi Taheri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin, Salvatore Pappalardo, Paul Jiménez, Bastien Deveautour, Alberto Bosio
2024	J	`jnl`	SAFFIRA: a Framework for Assessing the Reliability of Systolic-Array-Based DNN Accelerators. CoRR Mahdi Taheri, Masoud Daneshtalab, Jaan Raik, Maksim Jenihhin, Salvatore Pappalardo, Paul Jiménez, Bastien Deveautour, Alberto Bosio
2024	Misc	`conf`	Special Session: Reliability Assessment Recipes for DNN Accelerators. VTS Mohammad Hasan Ahmadilivani, Alberto Bosio, Bastien Deveautour, Fernando Fernandes dos Santos, Juan-David Guerrero-Balaguera, Maksim Jenihhin, Angeliki Kritikakou, Robert Limas Sierra, Salvatore Pappalardo, Jaan Raik, Josie E. Rodriguez Condia, Matteo Sonza Reorda, Mahdi Taheri, Marcello Traiola
2024	J	`jnl`	Syntactic and Semantic Analysis of Temporal Assertions to Support the Approximation of RTL Designs. J. Electron. Test. Alberto Bosio, Samuele Germiniani, Graziano Pravadelli, Marcello Traiola
2024	J	`jnl`	The Impact of Feature Representation on the Accuracy of Photonic Neural Networks. CoRR Mauricio Gomes de Queiroz, Paul Jiménez, Raphael Cardoso, Mateus Vidaletti Costa, Mohab Abdalla, Ian O'Connor, Alberto Bosio, Fabio Pavanello
2023	—	`conf`	A Fault Injection Framework for AI Hardware Accelerators. LATS Salvatore Pappalardo, Annachiara Ruospo, Ian O'Connor, Bastien Deveautour, Ernesto Sánchez, Alberto Bosio
2023	J	`jnl`	A Survey on Deep Learning Resilience Assessment Methodologies. Computer Annachiara Ruospo, Ernesto Sánchez, Lucas Matana Luza, Luigi Dilillo, Marcello Traiola, Alberto Bosio
2023	—	`conf`	Energy-efficient Computation-In-Memory Architecture using Emerging Technologies. ICM Rajendra Bishnoi, Sumit Diware, Anteneh Gebregiorgis, Simon Thomann, Sara Mannaa, Bastien Deveautour, Cédric Marchand, Alberto Bosio, Damien Deleruyelle, Ian O'Connor, Hussam Amrouch, Said Hamdioui
2023	A	`conf`	Exploiting assertions mining and fault analysis to guide RTL-level approximation. DATE Alberto Bosio, Samuele Germiniani, Graziano Pravadelli, Marcello Traiola
2023	C	`conf`	FeFET based Logic-in-Memory design methodologies, tools and open challenges. VLSI-SoC Cédric Marchand, Alban Nicolas, Paul-Antoine Matrangolo, David Navarro, Alberto Bosio, Ian O'Connor
2023	—	`ed.`	IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023, Juan-Les-Pins, France, October 3-5, 2023 DFT Luca Cassano, Mihalis Psarakis, Marcello Traiola, Alberto Bosio
2023	—	`conf`	Input-aware accuracy characterization for approximate circuits. DSN-W Ali Piri, Salvatore Pappalardo, Salvatore Barone, Mario Barbareschi, Bastien Deveautour, Marcello Traiola, Ian O'Connor, Alberto Bosio
2023	—	`conf`	Investigating the effect of approximate multipliers on the resilience of a systolic array DNN accelerator. DFT Salvatore Pappalardo, Ali Piri, Annachiara Ruospo, Ian O'Connor, Bastien Deveautour, Ernesto Sánchez, Alberto Bosio
2023	A	`conf`	Lightspeed Binary Neural Networks using Optical Phase-Change Materials. DATE Taha Shahroodi, Raphael Cardoso, Mahdi Zahedi, Stephan Wong, Alberto Bosio, Ian O'Connor, Said Hamdioui
2023	C	`conf`	Resilience-Performance Tradeoff Analysis of a Deep Neural Network Accelerator. DDECS Salvatore Pappalardo, Annachiara Ruospo, Ian O'Connor, Bastien Deveautour, Ernesto Sánchez, Alberto Bosio
2023	J	`jnl`	Special Issue on Approximate Computing: Challenges, Methodologies, Algorithms, and Architectures for Dependable and Secure Systems. IEEE Des. Test Alberto Bosio, Mario Barbareschi, Alessandro Savino, Jie Han, Jürgen Teich
2023	J	`jnl`	Special Issue: "Approximation at the Edge". ACM Trans. Embed. Comput. Syst. Alberto Bosio, Lara Dolecek, Alexandra Kourfali, Sri Parameswaran, Alessandro Savino
2023	Misc	`conf`	Special Session: Approximation and Fault Resiliency of DNN Accelerators. VTS Mohammad Hasan Ahmadilivani, Mario Barbareschi, Salvatore Barone, Alberto Bosio, Masoud Daneshtalab, Salvatore Della Torca, Gabriele Gavarini, Maksim Jenihhin, Jaan Raik, Annachiara Ruospo, Ernesto Sánchez, Mahdi Taheri
2023	J	`jnl`	Special Session: Approximation and Fault Resiliency of DNN Accelerators. CoRR Mohammad Hasan Ahmadilivani, Mario Barbareschi, Salvatore Barone, Alberto Bosio, Masoud Daneshtalab, Salvatore Della Torca, Gabriele Gavarini, Maksim Jenihhin, Jaan Raik, Annachiara Ruospo, Ernesto Sánchez, Mahdi Taheri
2023	Misc	`conf`	Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies. VTS Fabio Pavanello, Elena-Ioana Vatajelu, Alberto Bosio, Thomas Van Vaerenbergh, Peter Bienstman, Benoît Charbonnier, Alessio Carpegna, Stefano Di Carlo, Alessandro Savino
2023	J	`jnl`	Special Session: Neuromorphic hardware design and reliability from traditional CMOS to emerging technologies. CoRR Fabio Pavanello, Elena-Ioana Vatajelu, Alberto Bosio, Thomas Van Vaerenbergh, Peter Bienstman, Benoît Charbonnier, Alessio Carpegna, Stefano Di Carlo, Alessandro Savino
2022	C	`conf`	A Design Space Exploration Framework for Memristor-Based Crossbar Architecture. DDECS Mario Barbareschi, Alberto Bosio, Ian O'Connor, Petr Fiser, Marcello Traiola
2022	J	`jnl`	A Genetic-algorithm-based Approach to the Design of DCT Hardware Accelerators. ACM J. Emerg. Technol. Comput. Syst. Mario Barbareschi, Salvatore Barone, Alberto Bosio, Jie Han, Marcello Traiola
2022	—	`conf`	A Heuristic Exploration of Retraining-free Weight-Sharing for CNN Compression. ASP-DAC Etienne Dupuis, David Novo, Ian O'Connor, Alberto Bosio
2022	—	`conf`	A Logic Cell Design and routing Methodology Specific to VNWFET. NEWCAS Arnaud Poittevin, Ian O'Connor, Cédric Marchand, Alberto Bosio, Cristell Maneux, Chhandak Mukherjee, Guilhem Larrieu, Abhishek Kumar
2022	J	`jnl`	Approximations in Deep Learning. CoRR Etienne Dupuis, Silviu-Ioan Filip, Olivier Sentieys, David Novo, Ian O'Connor, Alberto Bosio
2022	—	`conf`	Assertion-aware approximate computing design exploration on behavioral models. LATS Alberto Bosio, Moreno Bragaglio, Samuele Germiniani, Samuele Mori, Graziano Pravadelli, Marcello Traiola
2022	C	`conf`	Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope? DDECS Cristiana Bolchini, Alberto Bosio, Luca Cassano, Bastien Deveautour, Giorgio Di Natale, Antonio Miele, Ian O'Connor, Elena-Ioana Vatajelu
2022	J	`jnl`	Emulating the Effects of Radiation-Induced Soft-Errors for the Reliability Assessment of Neural Networks. IEEE Trans. Emerg. Top. Comput. Lucas Matana Luza, Annachiara Ruospo, Daniel Söderström, Carlo Cazzaniga, Maria Kastriotou, Ernesto Sánchez, Alberto Bosio, Luigi Dilillo
2022	—	`conf`	Exploiting Approximate Computing for Efficient and Reliable Convolutional Neural Networks. ISVLSI Alberto Bosio, Bastien Deveautour, Ian O'Connor
2022	J	`jnl`	Guest Editorial: Computation-In-Memory (CIM): from Device to Applications. ACM J. Emerg. Technol. Comput. Syst. Said Hamdioui, Elena I. Vatajelu, Alberto Bosio
2022	—	`ed.`	IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022, Austin, TX, USA, October 19-21, 2022 DFT Luca Cassano, Sreejit Chakravarty, Alberto Bosio
2022	—	`conf`	Input-Aware Approximate Computing. AQTR Ali Piri, Sepide Saeedi, Mario Barbareschi, Bastien Deveautour, Stefano Di Carlo, Ian O'Connor, Alessandro Savino, Marcello Traiola, Alberto Bosio
2022	—	`conf`	Reliability assessment of FreeRTOS in Embedded Systems. DSN (Supplements) Alberto Bosio, Maurizio Rebaudengo, Alessandro Savino
2022	C	`conf`	Selective Hardening of Critical Neurons in Deep Neural Networks. DDECS Annachiara Ruospo, Gabriele Gavarini, Ilaria Bragaglia, Marcello Traiola, Alberto Bosio, Ernesto Sánchez
2022	—	`ch.`	Test and Reliability of Approximate Hardware. Approximate Computing Marcello Traiola, Bastien Deveautour, Alberto Bosio, Patrick Girard, Arnaud Virazel
2022	—	`conf`	Toward the hardening of real-time operating systems. DFT Alberto Bosio, Stefano Di Carlo, Maurizio Rebaudengo, Alessandro Savino
2021	C	`conf`	A Model-Based Framework to Assess the Reliability of Safety-Critical Applications. DDECS Lucas Matana Luza, Annachiara Ruospo, Alberto Bosio, Ernesto Sánchez, Luigi Dilillo
2021	C	`conf`	AdequateDL: Approximating Deep Learning Accelerators. DDECS Olivier Sentieys, Silviu-Ioan Filip, David Briand, David Novo, Etienne Dupuis, Ian O'Connor, Alberto Bosio
2021	—	`conf`	Approximate Computing for Safety-Critical Applications. LATS Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Alberto Bosio
2021	—	`conf`	Cell-Aware Diagnosis of Customer Returns Using Bayesian Inference. ISQED Safa Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, Aymen Ladhar
2021	A	`conf`	Design Space Exploration of Approximation-Based Quadruple Modular Redundancy Circuits. ICCAD Marcello Traiola, Jorge Echavarria, Alberto Bosio, Jürgen Teich, Ian O'Connor
2021	J	`jnl`	Editorial: Special issue on Advancing on Approximate Computing: Methodologies, Architectures and Algorithms. Future Gener. Comput. Syst. Mario Barbareschi, Alberto Bosio, Lukás Sekanina, Claus Braun
2021	C	`conf`	Efficient Neural Network Approximation via Bayesian Reasoning. DDECS Alessandro Savino, Marcello Traiola, Stefano Di Carlo, Alberto Bosio
2021	B	`conf`	Emerging Computing Devices: Challenges and Opportunities for Test and Reliability ETS Alberto Bosio, Ian O'Connor, Marcello Traiola, Jorge Echavarria, Jürgen Teich, Muhammad Abdullah Hanif, Muhammad Shafique, Said Hamdioui, Bastien Deveautour, Patrick Girard, Arnaud Virazel, Koen Bertels
2021	C	`conf`	Emerging Technologies: Challenges and Opportunities for Logic Synthesis. DDECS Alberto Bosio, Mayeul Cantan, Cédric Marchand, Ian O'Connor, Petr Fiser, Arnaud Poittevin, Marcello Traiola
2021	J	`jnl`	Fast Exploration of Weight Sharing Opportunities for CNN Compression. CoRR Etienne Dupuis, David Novo, Ian O'Connor, Alberto Bosio
2021	J	`jnl`	Investigating data representation for efficient and reliable Convolutional Neural Networks. Microprocess. Microsystems Annachiara Ruospo, Ernesto Sánchez, Marcello Traiola, Ian O'Connor, Alberto Bosio
2021	J	`jnl`	Multi-Objective Application-Driven Approximate Design Method. IEEE Access Salvatore Barone, Marcello Traiola, Mario Barbareschi, Alberto Bosio
2021	—	`conf`	Pros and Cons of Fault Injection Approaches for the Reliability Assessment of Deep Neural Networks. LATS Annachiara Ruospo, Lucas Matana Luza, Alberto Bosio, Marcello Traiola, Luigi Dilillo, Ernesto Sánchez
2021	Misc	`conf`	Special Session: Operating Systems under test: an overview of the significance of the operating system in the resiliency of the computing continuum. VTS Emmanuel Casseau, Petr Dobiás, Oliver Sinnen, Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Alessandro Savino, Stefano Di Carlo, Maurizio Rebaudengo, Alberto Bosio
2021	C	`conf`	Tutorial: Silicon Systems for Wireless LAN. DDECS Zoran Stamenkovic, Hassen Aziza, Ernesto Sánchez, Alberto Bosio
2020	A	`conf`	A Learning-Based Cell-Aware Diagnosis Flow for Industrial Customer Returns. ITC Safa Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, Aymen Ladhar
2020	—	`conf`	A Pipelined Multi-Level Fault Injector for Deep Neural Networks. DFT Annachiara Ruospo, Angelo Balaara, Alberto Bosio, Ernesto Sánchez
2020	J	`jnl`	A Survey of Testing Techniques for Approximate Integrated Circuits. Proc. IEEE Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2020	—	`conf`	Anytime Floating-Point Addition and Multiplication-Concepts and Implementations. ASAP Marcel Brand, Michael Witterauf, Alberto Bosio, Jürgen Teich
2020	—	`conf`	Cross-Layer Soft-Error Resilience Analysis of Computing Systems. DSN (Supplements) Alberto Bosio, Ramon Canal, Stefano Di Carlo, Dimitris Gizopoulos, Alessandro Savino
2020	B	`conf`	Design, Verification, Test and In-Field Implications of Approximate Computing Systems. ETS Alberto Bosio, Stefano Di Carlo, Patrick Girard, Ernesto Sánchez, Alessandro Savino, Lukás Sekanina, Marcello Traiola, Zdenek Vasícek, Arnaud Virazel
2020	—	`conf`	Effects of Thermal Neutron Irradiation on a Self-Refresh DRAM. DTIS Lucas Matana Luza, Daniel Söderström, Helmut Puchner, Rubén García Alía, Manon Letiche, Alberto Bosio, Luigi Dilillo
2020	C	`conf`	Evaluating Convolutional Neural Networks Reliability depending on their Data Representation. DSD Annachiara Ruospo, Alberto Bosio, Alessandro Ianne, Ernesto Sánchez
2020	—	`conf`	Exploiting Approximate Computing for implementing Low Cost Fault Tolerance Mechanisms. DTIS Alberto Bosio, Ian O'Connor, Gennaro Severino Rodrigues, Fernanda Lima Lima, Said Hamdioui
2020	—	`conf`	Investigating the Impact of Radiation-Induced Soft Errors on the Reliability of Approximate Computing Systems. DFT Lucas Matana Luza, Daniel Söderström, Georgios Tsiligiannis, Helmut Puchner, Carlo Cazzaniga, Ernesto Sánchez, Alberto Bosio, Luigi Dilillo
2020	B	`conf`	Learning-Based Cell-Aware Defect Diagnosis of Customer Returns. ETS Safa Mhamdi, Patrick Girard, Arnaud Virazel, Alberto Bosio, Aymen Ladhar
2020	A	`conf`	Maximizing Yield for Approximate Integrated Circuits. DATE Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2020	—	`conf`	On the Analysis of Real-time Operating System Reliability in Embedded Systems. DFT Dario Mamone, Alberto Bosio, Alessandro Savino, Said Hamdioui, Maurizio Rebaudengo
2020	A	`conf`	On the Automatic Exploration of Weight Sharing for Deep Neural Network Compression. DATE Etienne Dupuis, David Novo, Ian O'Connor, Alberto Bosio
2020	C	`conf`	Sensitivity Analysis and Compression Opportunities in DNNs Using Weight Sharing. DDECS Etienne Dupuis, David Novo, Ian O'Connor, Alberto Bosio
2019	—	`conf`	A Reliability Analysis of a Deep Neural Network. LATS Alberto Bosio, Paolo Bernardi, Annachiara Ruospo, Ernesto Sánchez
2019	B	`conf`	Alternatives to Fault Injections for Early Safety/Security Evaluations. ETS Michele Portolan, Alessandro Savino, Régis Leveugle, Stefano Di Carlo, Alberto Bosio, Giorgio Di Natale
2019	J	`jnl`	Assessing the Reliability of Successive Approximate Computing Algorithms under Fault Injection. J. Electron. Test. Gennaro Severino Rodrigues, Ádria Barros de Oliveira, Fernanda Lima Kastensmidt, Vincent Pouget, Alberto Bosio
2019	C	`conf`	Exploiting Approximate Computing to Increase System Lifetime. VLSI-SoC Alberto Bosio, Wilson-Javier Pérez-Holguín, Ernesto Sánchez
2019	—	`conf`	Exploiting approximate computing for low-cost fault tolerant architectures. SBCCI Gennaro Severino Rodrigues, Juan Fonseca, Fabio Benevenuti, Fernanda Lima Kastensmidt, Alberto Bosio
2019	A	`conf`	International Symposium on Design and Diagnostics of Electronic Circuits and Systems. ITC Zoran Stamenkovic, Alberto Bosio, György Cserey, Ondrej Novák, Witold A. Pleskacz, Lukás Sekanina, Andreas Steininger, Goran Stojanovic, Viera Stopjaková
2019	J	`jnl`	Memory-Aware Design Space Exploration for Reliability Evaluation in Computing Systems. J. Electron. Test. Maha Kooli, Giorgio Di Natale, Alberto Bosio
2019	—	`conf`	Rebooting Computing: The Challenges for Test and Reliability. DFT Alberto Bosio, Ian O'Connor, Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Elena I. Vatajelu, Giorgio Di Natale, Lorena Anghel, Surya Nagarajan, Moritz Fieback, Said Hamdioui
2019	J	`jnl`	Special Issue on Design, Technology, and Test of Integrated Circuits and Systems. J. Circuits Syst. Comput. Alberto Bosio, Mario Barbareschi
2019	J	`jnl`	SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems. IEEE Trans. Computers Alessandro Vallero, Alessandro Savino, Athanasios Chatzidimitriou, Manolis Kaliorakis, Maha Kooli, Marc Riera, Martí Anglada, Giorgio Di Natale, Alberto Bosio, Ramon Canal, Antonio González, Dimitris Gizopoulos, Riccardo Mariani, Stefano Di Carlo
2019	C	`conf`	Towards Improvement of Mission Mode Failure Diagnosis for System-on-Chip. IOLTS Safa Mhamdi, Arnaud Virazel, Patrick Girard, Alberto Bosio, Etienne Auvray, Eric Faehn, Aymen Ladhar
2018	—	`conf`	ARFT: An Approximative Redundant Technique for Fault Tolerance. DCIS Gennaro Severino Rodrigues, Ádria Barros de Oliveira, Alberto Bosio, Fernanda Lima Kastensmidt, Edison Pignaton de Freitas
2018	A	`conf`	An Effective Intra-Cell Diagnosis Flow for Industrial SRAMs. ITC Tien-Phu Ho, Eric Faehn, Arnaud Virazel, Alberto Bosio, Patrick Girard
2018	—	`conf`	Analyzing the Use of Taylor Series Approximation in Hardware and Embedded Software for Good Cost-Accuracy Tradeoffs. ARC Gennaro Severino Rodrigues, Ádria Barros de Oliveira, Fernanda Lima Kastensmidt, Alberto Bosio
2018	J	`jnl`	Estimating dynamic power consumption for memristor-based CiM architecture. Microelectron. Reliab. Marcello Traiola, Mario Barbareschi, Alberto Bosio
2018	—	`conf`	Exploring the inherent fault tolerance of successive approximation algorithms under laser fault injection. LATS Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Vincent Pouget, Alberto Bosio
2018	—	`conf`	Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits. DFT Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2018	C	`conf`	On the Comparison of Different ATPG Approaches for Approximate Integrated Circuits. DDECS Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2018	C	`conf`	Performances VS Reliability: how to exploit Approximate Computing for Safety-Critical applications. IOLTS Gennaro Severino Rodrigues, Fernanda Lima Kastensmidt, Vincent Pouget, Alberto Bosio
2018	C	`conf`	Predicting the Impact of Functional Approximation: from Component- to Application-Level. IOLTS Marcello Traiola, Alessandro Savino, Mario Barbareschi, Stefano Di Carlo, Alberto Bosio
2018	J	`jnl`	Scan-Chain Intra-Cell Aware Testing. IEEE Trans. Emerg. Top. Comput. Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda, Etienne Auvray
2018	Misc	`conf`	Special session: How approximate computing impacts verification, test and reliability. VTS Lukás Sekanina, Zdenek Vasícek, Alberto Bosio, Marcello Traiola, Paolo Rech, Daniel Oliveira, Fernando Fernandes, Stefano Di Carlo
2018	C	`conf`	Synthesis of Finite State Machines on Memristor Crossbars. DDECS Umberto Ferrandino, Marcello Traiola, Mario Barbareschi, Antonino Mazzeo, Petr Fiser, Alberto Bosio
2018	J	`jnl`	Test and Reliability in Approximate Computing. J. Electron. Test. Lorena Anghel, Mounir Benabdenbi, Alberto Bosio, Marcello Traiola, Elena-Ioana Vatajelu
2018	—	`conf`	Testing approximate digital circuits: Challenges and opportunities. LATS Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2017	J	`jnl`	A Cross-Level Power Estimation Technique to Enhance High-Level Power Models Quality. J. Low Power Electron. Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
2017	J	`jnl`	A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic Circuits. J. Electron. Test. Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
2017	—	`conf`	An effective fault-injection framework for memory reliability enhancement perspectives. DTIS G. Harcha, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi
2017	—	`conf`	Approximate computing: Design & test for integrated circuits. LATS Alberto Bosio, Arnaud Virazel, Patrick Girard, Mario Barbareschi
2017	J	`jnl`	Computing reliability: On the differences between software testing and software fault injection techniques. Microprocess. Microsystems Maha Kooli, Firas Kaddachi, Giorgio Di Natale, Alberto Bosio, Pascal Benoit, Lionel Torres
2017	C	`conf`	Formal Design Space Exploration for memristor-based crossbar architecture. DDECS Marcello Traiola, Mario Barbareschi, Alberto Bosio
2017	J	`jnl`	HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power Characterization. J. Circuits Syst. Comput. Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
2017	—	`conf`	Memristive devices: Technology, design automation and computing frontiers. DTIS Mario Barbareschi, Alberto Bosio, Hoang Anh Du Nguyen, Said Hamdioui, Marcello Traiola, Elena-Ioana Vatajelu
2017	J	`jnl`	Microprocessor Testing: Functional Meets Structural Test. J. Circuits Syst. Comput. Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2017	C	`conf`	Reliability of computing systems: From flip flops to variables. IOLTS Giorgio Di Natale, Maha Kooli, Alberto Bosio, Michele Portolan, Régis Leveugle
2017	C	`conf`	Towards approximation during test of Integrated Circuits. DDECS Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2017	—	`conf`	Towards digital circuit approximation by exploiting fault simulation. EWDTS Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
2016	J	`jnl`	A Hybrid Fault-Tolerant Architecture for Highly Reliable Processing Cores. J. Electron. Test. Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Matteo Sonza Reorda
2016	C	`conf`	A Hybrid Power Estimation Technique to improve IP power models quality. VLSI-SoC Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
2016	C	`conf`	A hybrid power modeling approach to enhance high-level power models. DDECS Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
2016	B	`conf`	A low-cost susceptibility analysis methodology to selectively harden logic circuits. ETS Imran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
2016	—	`conf`	An effective BIST architecture for power-gating mechanisms in low-power SRAMs. ISQED Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Leonardo Bonet Zordan
2016	C	`conf`	An effective approach for functional test programs compaction. DDECS Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2016	—	`conf`	Analysis of setup and hold margins inside silicon for advanced technology nodes. ISQED Deepak-Kumar Arora, Darayus Adil Patel, Shahabuddin, Sanjay Kumar, Navin Kumar Dayani, Balwant Singh, Sylvie Naudet, Arnaud Virazel, Alberto Bosio
2016	—	`conf`	Auto-adaptive ultra-low power IC. DTIS Alberto Bosio, Philippe Debaud, Patrick Girard, Stephane Guilhot, Miroslav Valka, Arnaud Virazel
2016	Misc	`conf`	Cache- and register-aware system reliability evaluation based on data lifetime analysis. VTS Maha Kooli, Firas Kaddachi, Giorgio Di Natale, Alberto Bosio
2016	C	`conf`	Cache-aware reliability evaluation through LLVM-based analysis and fault injection. IOLTS Maha Kooli, Giorgio Di Natale, Alberto Bosio
2016	A	`conf`	Cross-layer system reliability assessment framework for hardware faults. ITC Alessandro Vallero, Alessandro Savino, Gianfranco Politano, Stefano Di Carlo, Athanasios Chatzidimitriou, Sotiris Tselonis, Manolis Kaliorakis, Dimitris Gizopoulos, Marc Riera, Ramon Canal, Antonio González, Maha Kooli, Alberto Bosio, Giorgio Di Natale
2016	J	`jnl`	Design for Test and Diagnosis of Power Switches. J. Circuits Syst. Comput. Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Philippe Debaud, Stephane Guilhot
2016	C	`conf`	Faster-than-at-speed execution of functional programs: An experimental analysis. VLSI-SoC Paolo Bernardi, Alberto Bosio, Giorgio Di Natale, Andrea Guerriero, Federico Venini
2016	—	`conf`	Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs. VLSI-SoC (Selected Papers) Paolo Bernardi, Alberto Bosio, Giorgio Di Natale, Andrea Guerriero, Ernesto Sánchez, Federico Venini
2016	—	`conf`	Improving the Functional Test Delay Fault Coverage: A Microprocessor Case Study. ISVLSI Aymen Touati, Alberto Bosio, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2016	C	`conf`	System-level reliability evaluation through cache-aware software-based fault injection. DDECS Firas Kaddachi, Maha Kooli, Giorgio Di Natale, Alberto Bosio, Mojtaba Ebrahimi, Mehdi Baradaran Tahoori
2016	—	`conf`	Test of low power circuits: Issues and industrial practices. ICECS Alberto Bosio, Patrick Girard, Arnaud Virazel
2016	Misc	`conf`	Thermal issues in test: An overview of the significant aspects and industrial practice. VTS Juergen Alt, Paolo Bernardi, Alberto Bosio, Riccardo Cantoro, Hans G. Kerkhoff, Andreas Leininger, Wolfgang Molzer, Alessandro Motta, Christian Pacha, Alberto Pagani, Alireza Rohani, R. Strasser
2016	C	`conf`	XbarGen: A memristor based boolean logic synthesis tool. VLSI-SoC Marcello Traiola, Mario Barbareschi, Antonino Mazzeo, Alberto Bosio
2015	—	`conf`	An ATPG Flow to Generate Crosstalk-Aware Path Delay Pattern. ISVLSI Anu Asokan, Alberto Bosio, Arnaud Virazel, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch
2015	—	`conf`	An effective ATPG flow for Gate Delay Faults. DTIS Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2015	B	`conf`	An effective hybrid fault-tolerant architecture for pipelined cores. ETS Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard
2015	—	`conf`	An efficient hybrid power modeling approach for accurate gate-level power estimation. ICM Alejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard, Cyril Chevalier
2015	J	`jnl`	Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview. Microprocess. Microsystems Alessandro Vallero, Sotiris Tselonis, Nikos Foutris, Manolis Kaliorakis, Maha Kooli, Alessandro Savino, Gianfranco Politano, Alberto Bosio, Giorgio Di Natale, Dimitris Gizopoulos, Stefano Di Carlo
2015	—	`conf`	Design and performance parameters of an ultra-low voltage, single supply 32bit processor implemented in 28nm FDSOI technology. ISQED Sylvain Clerc, Fady Abouzeid, Darayus Adil Patel, Jean-Marc Daveau, Cyril Bottoni, Lorenzo Ciampolini, Fabien Giner, David Meyer, Robin Wilson, Philippe Roche, Sylvie Naudet, Arnaud Virazel, Alberto Bosio, Patrick Girard
2015	C	`conf`	Design space exploration and optimization of a Hybrid Fault-Tolerant Architecture. IOLTS Imran Wali, Arnaud Virazel, Alberto Bosio, Patrick Girard, Matteo Sonza Reorda
2015	C	`conf`	Design-for-Diagnosis Architecture for Power Switches. DDECS Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, P. Debaud, S. Guilhot
2015	A	`conf`	Exploring the impact of functional test programs re-used for power-aware testing. DATE Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2015	—	`conf`	Scan-chain intra-cell defects grading. DTIS Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda
2015	—	`conf`	Software testing and software fault injection. DTIS Maha Kooli, Alberto Bosio, Pascal Benoit, Lionel Torres
2014	J	`jnl`	A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs. IEEE Trans. Very Large Scale Integr. Syst. Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Jérémy Alvarez-Herault, Ken Mackay
2014	—	`conf`	A Comprehensive Evaluation of Functional Programs for Power-Aware Test. NATW Aymen Touati, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, Paolo Bernardi
2014	—	`conf`	A Delay Probability Metric for Input Pattern Ranking Under Process Variation and Supply Noise. ISVLSI Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2014	J	`jnl`	A New Hybrid Fault-Tolerant Architecture for Digital CMOS Circuits and Systems. J. Electron. Test. D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
2014	B	`conf`	A novel adaptive fault tolerant flip-flop architecture based on TMR. ETS Luca Cassano, Alberto Bosio, Giorgio Di Natale
2014	C	`conf`	An intra-cell defect grading tool. DDECS Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Arnaud Virazel, S. Bernabovi, Paolo Bernardi
2014	J	`jnl`	Globally Constrained Locally Optimized 3-D Power Delivery Networks. IEEE Trans. Very Large Scale Integr. Syst. Aida Todri-Sanial, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel
2014	J	`jnl`	Intra-Cell Defects Diagnosis. J. Electron. Test. Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Etienne Auvray
2014	—	`conf`	On the Generation of Diagnostic Test Set for Intra-cell Defects. ATS Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Etienne Auvray
2014	J	`jnl`	On the Test and Mitigation of Malfunctions in Low-Power SRAMs. J. Electron. Test. Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Nabil Badereddine
2014	C	`conf`	Path delay test in the presence of multi-aggressor crosstalk, power supply noise and ground bounce. DDECS Anu Asokan, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2014	—	`conf`	Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration. ASP-DAC Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
2014	C	`conf`	Protecting combinational logic in pipelined microprocessor cores against transient and permanent faults. DDECS Imran Wali, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri
2014	Misc	`conf`	TSV aware timing analysis and diagnosis in paths with multiple TSVs. VTS Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
2014	C	`conf`	Test and diagnosis of power switches. DDECS Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot
2014	C	`conf`	Timing-aware ATPG for critical paths with multiple TSVs. DDECS Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
2014	B	`conf`	iBoX - Jitter based Power Supply Noise sensor. ETS Miroslav Valka, Alberto Bosio, Luigi Dilillo, Aida Todri, Arnaud Virazel, Patrick Girard, P. Debaud, S. Guilhot
2013	J	`jnl`	A Study of Tapered 3-D TSVs for Power and Thermal Integrity. IEEE Trans. Very Large Scale Integr. Syst. Aida Todri, Sandip Kundu, Patrick Girard, Alberto Bosio, Luigi Dilillo, Arnaud Virazel
2013	Misc	`conf`	A built-in scheme for testing and repairing voltage regulators of low-power srams. VTS Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	—	`conf`	A novel method to mitigate TSV electromigration for 3D ICs. ISVLSI Yuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dillio, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville
2013	—	`conf`	Adaptive Source Bias for Improved Resistive-Open Defect Coverage during SRAM Testing. Asian Test Symposium Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	B	`conf`	Analyzing resistive-open defects in SRAM core-cell under the effect of process variability. ETS Elena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	—	`conf`	Analyzing the effect of concurrent variability in the core cells and sense amplifiers on SRAM read access failures. DTIS Elena I. Vatajelu, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	—	`conf`	Characterization of an SRAM based particle detector for mixed-field radiation environments. IWASI Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri-Sanial, Arnaud Virazel, Julien Mekki, Markus Brugger, J.-R. Vaillé, Frederic Wrobel, Frédéric Saigné
2013	B	`conf`	Computing detection probability of delay defects in signal line tsvs. ETS Carolina Metzler, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel, Pascal Vivet, Marc Belleville
2013	—	`conf`	Effect-cause intra-cell diagnosis at transistor level. ISQED Zhenzhou Sun, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Etienne Auvray
2013	J	`jnl`	Fast Power Evaluation for Effective Generation of Test Programs Maximizing Peak Power Consumption. J. Low Power Electron. Paolo Bernardi, Mauricio de Carvalho, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Miroslav Valka, Patrick Girard
2013	—	`conf`	On the correlation between Static Noise Margin and Soft Error Rate evaluated for a 40nm SRAM cell. DFTS Elena I. Vatajelu, Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné
2013	A	`conf`	On the reuse of read and write assist circuits to improve test efficiency in low-power SRAMs. ITC Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	C	`conf`	SRAM soft error rate evaluation under atmospheric neutron radiation and PVT variations. IOLTS Georgios Tsiligiannis, Elena I. Vatajelu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Frederic Wrobel, Frédéric Saigné
2013	A	`conf`	Test solution for data retention faults in low-power SRAMs. DATE Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2013	J	`jnl`	Uncorrelated Power Supply Noise and Ground Bounce Consideration for Test Pattern Generation. IEEE Trans. Very Large Scale Integr. Syst. Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
2013	—	`conf`	Worst-case power supply noise and temperature distribution analysis for 3D PDNs with multiple clock domains. NEWCAS Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2012	Misc	`conf`	A pseudo-dynamic comparator for error detection in fault tolerant architectures. VTS D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Michael E. Imhof, Hans-Joachim Wunderlich
2012	Misc	`conf`	Advanced test methods for SRAMs. VTS Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2012	J	`jnl`	Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTAC J. Electron. Test. Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
2012	B	`conf`	Coupling-based resistive-open defects in TAS-MRAM architectures. ETS Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay
2012	B	`conf`	Defect analysis in power mode control logic of low-power SRAMs. ETS Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2012	C	`conf`	Evaluation of test algorithms stress effect on SRAMs under neutron radiation. IOLTS Georgios Tsiligiannis, Luigi Dilillo, Alberto Bosio, Patrick Girard, Aida Todri, Arnaud Virazel, Antoine D. Touboul, Frederic Wrobel, Frédéric Saigné
2012	—	`conf`	Impact of Resistive-Bridge Defects in TAS-MRAM Architectures. Asian Test Symposium Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay
2012	J	`jnl`	Impact of Resistive-Bridging Defects in SRAM at Different Technology Nodes. J. Electron. Test. Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2012	A	`conf`	Impact of resistive-open defects on the heat current of TAS-MRAM architectures. DATE Joao Azevedo, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri-Sanial, Guillaume Prenat, Jérémy Alvarez-Herault, Ken Mackay
2012	A	`conf`	Low-power SRAMs power mode control logic: Failure analysis and test solutions. ITC Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Nabil Badereddine
2012	—	`conf`	Peak Power Estimation: A Case Study on CPU Cores. Asian Test Symposium Paolo Bernardi, Mauricio de Carvalho, Ernesto Sánchez, Matteo Sonza Reorda, Alberto Bosio, Luigi Dilillo, Patrick Girard, Miroslav Valka
2012	—	`conf`	Power Supply Noise Sensor Based on Timing Uncertainty Measurements. Asian Test Symposium Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, P. Debaud, S. Guilhot
2012	J	`jnl`	Statistical Reliability Estimation of Microprocessor-Based Systems. IEEE Trans. Computers Alessandro Savino, Stefano Di Carlo, Gianfranco Politano, Alfredo Benso, Alberto Bosio, Giorgio Di Natale
2012	B	`conf`	Through-Silicon-Via resistive-open defect analysis. ETS Carolina Metzler, Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel
2012	—	`conf`	Why and How Controlling Power Consumption during Test: A Survey. Asian Test Symposium Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel
2011	B	`conf`	A Functional Power Evaluation Flow for Defining Test Power Limits during At-Speed Delay Testing. ETS Miroslav Valka, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Ernesto Sánchez, Mauricio de Carvalho, Matteo Sonza Reorda
2011	—	`conf`	A Hybrid Fault Tolerant Architecture for Robustness Improvement of Digital Circuits. Asian Test Symposium D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
2011	C	`conf`	A study of path delay variations in the presence of uncorrelated power and ground supply noise. DDECS Aida Todri, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2011	—	`conf`	Effective Launch-to-Capture Power Reduction for LOS Scheme with Adjacent-Probability-Based X-Filling. Asian Test Symposium Kohei Miyase, Y. Uchinodan, Kazunari Enokimoto, Yuta Yamato, Xiaoqing Wen, Seiji Kajihara, Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Arnaud Virazel
2011	—	`conf`	Error Resilient Infrastructure for Data Transfer in a Distributed Neutron Detector. DFT Luigi Dilillo, Alberto Bosio, Miroslav Valka, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2011	—	`conf`	Failure Analysis and Test Solutions for Low-Power SRAMs. Asian Test Symposium Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Aida Todri, Arnaud Virazel, Nabil Badereddine
2011	—	`conf`	On the Modeling of Gate Delay Faults by Means of Transition Delay Faults. DFT Paolo Bernardi, Matteo Sonza Reorda, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch
2011	C	`conf`	On using a SPICE-like TSTAC™ eFlash model for design and test. DDECS Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
2011	A	`conf`	On using address scrambling to implement defect tolerance in SRAMs. ITC Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2011	C	`conf`	Optimized march test flow for detecting memory faults in SRAM devices under bit line coupling. DDECS Leonardo Bonet Zordan, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2011	—	`conf`	Power-Aware Test Pattern Generation for At-Speed LOS Testing. Asian Test Symposium Alberto Bosio, Luigi Dilillo, Patrick Girard, Aida Todri, Arnaud Virazel, Kohei Miyase, Xiaoqing Wen
2010	J	`jnl`	A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for Launch-Off-Shift and Launch-Off-Capture Schemes. J. Low Power Electron. Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Xiaoqing Wen, Nisar Ahmed
2010	J	`jnl`	A Comprehensive Framework for Logic Diagnosis of Arbitrary Defects. IEEE Trans. Computers Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel
2010	—	`conf`	A Comprehensive System-on-Chip Logic Diagnosis. Asian Test Symposium Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer
2010	—	`conf`	A Memory Fault Simulator for Radiation-Induced Effects in SRAMs. Asian Test Symposium Paolo Rech, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Luigi Dilillo
2010	A*	`conf`	A statistical simulation method for reliability analysis of SRAM core-cells. DAC Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010	B	`conf`	A two-layer SPICE model of the ATMEL TSTAC ETS Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard, Gilles Festes, Laurent Vachez
2010	—	`conf`	An Exact and Efficient Critical Path Tracing Algorithm. DELTA Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda
2010	C	`conf`	Analysis of power consumption and transition fault coverage for LOS and LOC testing schemes. DDECS Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Junxia Ma, Wei Zhao, Mohammad Tehranipoor, Xiaoqing Wen
2010	B	`conf`	Analysis of resistive-bridging defects in SRAM core-cells: A comparative study from 90nm down to 40nm technology nodes. ETS Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010	Misc	`conf`	Detecting NBTI induced failures in SRAM core-cells. VTS Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010	—	`conf`	Impact of Resistive-Bridging Defects in SRAM Core-Cell. DELTA Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2010	A	`conf`	Is test power reduction through X-filling good enough? ITC Fangmei Wu, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Mohammad Tehranipoor, Kohei Miyase, Xiaoqing Wen, Nisar Ahmed
2010	A	`conf`	Parity prediction synthesis for nano-electronic gate designs. ITC D. A. Tran, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Hans-Joachim Wunderlich
2010	B	`conf`	Setting test conditions for improving SRAM reliability. ETS Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine
2009	—	`conf`	A case study on logic diagnosis for System-on-Chip. ISQED Youssef Benabboud, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute
2009	J	`jnl`	A dynamic programming algorithm for the single-machine scheduling problem with release dates and deteriorating processing times. Math. Methods Oper. Res. Alberto Bosio, Giovanni Righini
2009	C	`conf`	An efficient fault simulation technique for transition faults in non-scan sequential circuits. DDECS Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi, Matteo Sonza Reorda
2009	J	`jnl`	Are IEEE-1500-Compliant Cores Really Compliant to the Standard?. IEEE Des. Test Comput. Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Paolo Prinetto
2009	C	`conf`	Comprehensive bridging fault diagnosis based on the SLAT paradigm. DDECS Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute
2009	—	`conf`	Delay Fault Diagnosis in Sequential Circuits. Asian Test Symposium Youssef Benabboud, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Olivia Riewer
2009	J	`jnl`	Is triple modular redundancy suitable for yield improvement? IET Comput. Digit. Tech. Julien Vial, Arnaud Virazel, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch
2009	A	`conf`	NAND flash testing: A preliminary study on actual defects. ITC Pierre-Didier Mauroux, Arnaud Virazel, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Benoît Godard
2008	A	`conf`	A History-Based Diagnosis Technique for Static and Dynamic Faults in SRAMs. ITC Alexandre Ney, Alberto Bosio, Luigi Dilillo, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Magali Bastian
2008	C	`conf`	A Modular Memory BIST for Optimized Memory Repair. IOLTS Philipp Öhler, Alberto Bosio, Giorgio Di Natale, Sybille Hellebrand
2008	—	`conf`	Improving Diagnosis Resolution without Physical Information. DELTA Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2008	—	`conf`	LIFTING: A Flexible Open-Source Fault Simulator. ATS Alberto Bosio, Giorgio Di Natale
2008	J	`jnl`	March Test Generation Revealed. IEEE Trans. Computers Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2008	C	`conf`	SoC Symbolic Simulation: a case study on delay fault testing. DDECS Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Paolo Bernardi
2008	A	`conf`	SoC Yield Improvement: Redundant Architectures to the Rescue? ITC Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2008	—	`conf`	Using TMR Architectures for Yield Improvement. DFT Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2008	C	`conf`	Yield Improvement, Fault-Tolerance to the Rescue?. IOLTS Julien Vial, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	—	`conf`	A Functional Verification Based Fault Injection Environment. DFT Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Riccardo Mariani
2007	C	`conf`	A Mixed Approach for Unified Logic Diagnosis. DDECS Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	—	`conf`	Automating the IEEE std.1500 compliance verification for embedded cores. HLDVT Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Alberto Bosio
2007	B	`conf`	DERRIC: A Tool for Unified Logic Diagnosis. ETS Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	—	`conf`	Fast Bridging Fault Diagnosis using Logic Information. ATS Alexandre Rousset, Alberto Bosio, Patrick Girard, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel
2007	J	`jnl`	March AB, a state-of-the-art march test for realistic static linked faults and dynamic faults in SRAMs. IET Comput. Digit. Tech. Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2006	B	`conf`	A 22n March Test for Realistic Static Linked Faults in SRAMs. ETS Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2006	C	`conf`	A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs. DDECS Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2006	J	`jnl`	A dynamic programming algorithm for the single-machine scheduling problem with deteriorating processing times. Electron. Notes Discret. Math. Alberto Bosio, Giovanni Righini
2006	—	`conf`	ATPG for Dynamic Burn-In Test in Full-Scan Circuits. ATS Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2006	—	`conf`	Automatic March Tests Generation for Multi-Port SRAMs. DELTA Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2006	A	`conf`	Automatic march tests generations for static linked faults in SRAMs. DATE Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2006	—	`conf`	Memory Fault Simulator for Static-Linked Faults. ATS Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2005	B	`conf`	Automatic March tests generation for static and dynamic faults in SRAMs. ETS Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto
2005	A	`conf`	March AB, March AB1: new March tests for unlinked dynamic memory faults. ITC Alfredo Benso, Alberto Bosio, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto