Albert R. Wang

20 papers A* 5A 4C 1Journal 9Unranked 1
YearRankTypeTitle / Venue / Authors
2001 C conf
Matching Architecture to Application Via Configurable Processors: A Case Study with Boolean Satisfiability Problem.
ICCD
Ying Zhao, Sharad Malik, Albert R. Wang, Matthew W. Moskewicz, Conor F. Madigan
1998 J jnl
Code Optimization Techniques in Embedded DSP Microprocessors.
Des. Autom. Embed. Syst.
Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert R. Wang
1996 J jnl
Storage Assignment to Decrease Code Size.
ACM Trans. Program. Lang. Syst.
Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert R. Wang
1995 A* conf
A Design and Validation System for Asynchronous Circuits.
DAC
Peter Vanbekbergen, Albert R. Wang, Kurt Keutzer
1995 A* conf
Code Optimization Techniques for Embedded DSP Microprocessors.
DAC
Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert R. Wang
1995 A* conf
Storage Assignment to Decrease Code Size.
PLDI
Stan Y. Liao, Srinivas Devadas, Kurt Keutzer, Steven W. K. Tjiang, Albert R. Wang
1994 J jnl
Certified timing verification and the transition delay of a logic circuit.
IEEE Trans. Very Large Scale Integr. Syst.
Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang
1994 — conf
Challenges in code generation for embedded processors.
Code Generation for Embedded Processors
Guido Araujo, Srinivas Devadas, Kurt Keutzer, Stan Y. Liao, Sharad Malik, Ashok Sudarsanam, Steven W. K. Tjiang, Albert R. Wang
1994 J jnl
Event suppression: improving the efficiency of timing simulation for synchronous digital circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang
1994 J jnl
Verification of asynchronous interface circuits with bounded wire delays.
J. VLSI Signal Process.
Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang
1993 J jnl
Computation of floating mode delay in combinational circuits: practice and implementation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang
1992 A* conf
Certified Timing Verification and the Transition Delay of a Logic Circuit.
DAC
Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang
1992 A conf
Verification of asynchronous interface circuits with bounded wire delays.
ICCAD
Srinivas Devadas, Kurt Keutzer, Sharad Malik, Albert R. Wang
1989 J jnl
Boolean decomposition in multilevel logic optimization.
IEEE J. Solid State Circuits
Srinivas Devadas, Albert R. Wang, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1989 A* conf
Multi-level Logic Simplification Using Don't Cares and Filters.
DAC
Alexander Saldanha, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1988 A conf
Boolean decomposition in multi-level logic optimization.
ICCAD
Srinivas Devadas, Albert R. Wang, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli
1988 A conf
Logic verification using binary decision diagrams in a logic synthesis environment.
ICCAD
Sharad Malik, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1988 J jnl
Multi-level logic minimization using implicit don't cares.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Karen A. Bartlett, Robert K. Brayton, Gary D. Hachtel, Reily M. Jacoby, Christopher R. Morrison, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang
1988 A conf
Timing optimization of combinational logic.
ICCAD
Kanwar Jit Singh, Albert R. Wang, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli
1987 J jnl
MIS: A Multiple-Level Logic Optimization System.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Robert K. Brayton, Richard L. Rudell, Alberto L. Sangiovanni-Vincentelli, Albert R. Wang