Alan Mishchenko

171 papers A* 21A 52B 13C 3Misc 2Journal 45Unranked 34

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Scalable Sequential Logic Synthesis Using Observability Don't Care Conditions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dewmini Sudara Marakkalage, Eleonora Testa, Giulia Meuli, Walter Lau Neto, Alan Mishchenko, Giovanni De Micheli, Luca G. Amarù
2025	—	`conf`	Area-Oriented Optimization After Standard-Cell Mapping. ASP-DAC Andrea Costamagna, Alessandro Tempia Calvino, Alan Mishchenko, Giovanni De Micheli
2025	J	`jnl`	Area-Oriented Resubstitution For Networks of Look-Up Tables. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Andrea Costamagna, Alessandro Tempia Calvino, Alan Mishchenko, Giovanni De Micheli
2025	J	`jnl`	Efficient Resubstitution-Based Approximate Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Chang Meng, Alan Mishchenko, Weikang Qian, Giovanni De Micheli
2025	J	`jnl`	Enhancing Delay-Driven LUT Mapping With Boolean Decomposition. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alessandro Tempia Calvino, Giovanni De Micheli, Alan Mishchenko, Robert K. Brayton
2025	—	`conf`	High-Effort Logic Synthesis Using Randomized Transduction. ASP-DAC Yukio Miyasaka, Alan Mishchenko, John Wawrzynek, Dino Ruic, Xiaoqing Xu
2025	—	`conf`	ML-Inspired Logic Synthesis: Improving Multiplier Circuits. MLCAD Yukio Miyasaka, Walter Lau Neto, Eleonora Testa, Anika Prasad, Michael Shuster, Reto Zimmermann, Patrick Vuillod, Alan Mishchenko, John Wawrzynek, Luca G. Amarù
2025	A	`conf`	SimGen: Simulation Pattern Generation for Efficient Equivalence Checking. DATE Carmine Rizzi, Sarah Brunner, Alan Mishchenko, Lana Josipovic
2025	Misc	`conf`	Symmetry-Based Synthesis for Interpretable Boolean Evaluation. VLSID Andrea Costamagna, Alan Mishchenko, Satrajit Chatterjee, Giovanni De Micheli
2025	A	`conf`	Versatile Rewiring and Concurrent Resynthesis for High-Quality Customized Optimization. ICCAD Jiun-Hao Chen, Jie-Hong R. Jiang, Alan Mishchenko
2024	C	`conf`	An Enhanced Resubstitution Algorithm for Area-Oriented Logic Optimization. ISCAS Andrea Costamagna, Alan Mishchenko, Satrajit Chatterjee, Giovanni De Micheli
2024	J	`jnl`	DAG-Aware Synthesis Orchestration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yingjie Li, Mingju Liu, Haoxing Ren, Alan Mishchenko, Cunxi Yu
2024	—	`conf`	High Quality Circuit-Based 3-SAT Mappings for Oscillator Ising Machines. UCNC Venkata Pavan Sumanth Sikhakollu, Shreesha Sreedhara, Rajit Manohar, Alan Mishchenko, Jaijeet Roychowdhury
2024	J	`jnl`	Practical Boolean Decomposition for Delay-driven LUT Mapping. CoRR Alessandro Tempia Calvino, Alan Mishchenko, Giovanni De Micheli, Robert K. Brayton
2024	A	`conf`	Scalable Sequential Optimization Under Observability Don't Cares. DATE Dewmini Sudara Marakkalage, Eleonora Testa, Walter Lau Neto, Alan Mishchenko, Giovanni De Micheli, Luca G. Amarù
2024	Misc	`conf`	Synthesis of LUT Networks for Random-Looking Dense Functions with Don't Cares - Towards Efficient FPGA Implementation of DNN. FCCM Yukio Miyasaka, Alan Mishchenko, John Wawrzynek, Nicholas J. Fraser
2023	J	`jnl`	DAG-aware Synthesis Orchestration. CoRR Yingjie Li, Mingju Liu, Mark Ren, Alan Mishchenko, Cunxi Yu
2023	A*	`conf`	Improving Standard-Cell Design Flow using Factored Form Optimization. DAC Alessandro Tempia Calvino, Alan Mishchenko, Herman Schmit, Ethan Mahintorabi, Giovanni De Micheli, Xiaoqing Xu
2023	A	`conf`	Invited Paper: Verilog-to-PyG - A Framework for Graph Learning and Augmentation on RTL Designs. ICCAD Yingjie Li, Mingju Liu, Alan Mishchenko, Cunxi Yu
2023	A	`conf`	Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the Industry. DATE Benjamin Lukas Cajus Barzen, Arya Reais-Parsi, Eddie Hung, Minwoo Kang, Alan Mishchenko, Jonathan W. Greene, John Wawrzynek
2023	J	`jnl`	Quantized Neural Network Synthesis for Direct Logic Circuit Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yu-Shan Huang, Jie-Hong R. Jiang, Alan Mishchenko
2023	J	`jnl`	Scalable Sequential Optimization Under Observability Don't Cares. CoRR Dewmini Sudara Marakkalage, Eleonora Testa, Walter Lau Neto, Alan Mishchenko, Giovanni De Micheli, Luca G. Amarù
2023	J	`jnl`	Verilog-to-PyG - A Framework for Graph Learning and Augmentation on RTL Designs. CoRR Yingjie Li, Mingju Liu, Alan Mishchenko, Cunxi Yu
2022	J	`jnl`	A Simulation-Guided Paradigm for Logic Synthesis and Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli
2022	—	`conf`	Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis. ASP-DAC Heinz Riener, Siang-Yun Lee, Alan Mishchenko, Giovanni De Micheli
2022	A*	`conf`	Improving LUT-based optimization for ASICs. DAC Walter Lau Neto, Luca G. Amarù, Vinicius Possani, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon
2021	A	`conf`	A Circuit-Based SAT Solver for Logic Synthesis. ICCAD He-Teng Zhang, Jie-Hong R. Jiang, Alan Mishchenko
2021	A*	`conf`	Deep Integration of Circuit Simulator and SAT Solver. DAC He-Teng Zhang, Jie-Hong R. Jiang, Luca G. Amarù, Alan Mishchenko, Robert K. Brayton
2021	A*	`conf`	LUT-Based Optimization For ASIC Design Flow. DAC Luca Gaetano Amarù, Vinicius N. Possani, Eleonora Testa, Felipe S. Marranghello, Christopher Casares, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli
2021	A	`conf`	Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. DATE Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa, Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
2021	J	`jnl`	Three-Input Gates for Logic Synthesis. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Dewmini Sudara Marakkalage, Eleonora Testa, Heinz Riener, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli
2020	A*	`conf`	ALSRAC: Approximate Logic Synthesis by Resubstitution with Approximate Care Set. DAC Chang Meng, Weikang Qian, Alan Mishchenko
2020	A*	`conf`	Circuit-Based Intrinsic Methods to Detect Overfitting. ICML Satrajit Chatterjee, Alan Mishchenko
2020	A	`conf`	Exact DAG-Aware Rewriting. DATE Heinz Riener, Alan Mishchenko, Mathias Soeken
2020	J	`jnl`	Extending Boolean Methods for Scalable Logic Synthesis. IEEE Access Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2020	J	`jnl`	Fast Exact NPN Classification by Co-Designing Canonical Form and Its Computation Algorithm. IEEE Trans. Computers Xuegong Zhou, Lingli Wang, Alan Mishchenko
2020	—	`conf`	Keynote III: Boolean Logic Networks for Machine Learning. ISMVL Alan Mishchenko
2020	J	`jnl`	Logic Synthesis Meets Machine Learning: Trading Exactness for Generalization. CoRR Shubham Rai, Walter Lau Neto, Yukio Miyasaka, Xinpei Zhang, Mingfei Yu, Qingyang Yi, Masahiro Fujita, Guilherme B. Manske, Matheus F. Pontes, Leomar S. da Rosa Jr., Marilton S. de Aguiar, Paulo F. Butzen, Po-Chun Chien, Yu-Shan Huang, Hoa-Ren Wang, Jie-Hong R. Jiang, Jiaqi Gu, Zheng Zhao, Zixuan Jiang, David Z. Pan, Brunno A. Abreu, Isac de Souza Campos, Augusto Andre Souza Berndt, Cristina Meinhardt, Jônata Tyska Carvalho, Mateus Grellert, Sergio Bampi, Aditya Lohana, Akash Kumar, Wei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu, Yuan Zhou, Jordan Dotzel, Yichi Zhang, Hanyu Wang, Zhiru Zhang, Valerio Tenace, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Satrajit Chatterjee
2020	J	`jnl`	Parallel Combinational Equivalence Checking. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Vinicius N. Possani, Alan Mishchenko, Renato P. Ribas, André Inácio Reis
2020	J	`jnl`	SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Winston Haaswijk, Mathias Soeken, Alan Mishchenko, Giovanni De Micheli
2020	—	`conf`	SAT-Based Mapping of Data-Flow Graphs onto Coarse-Grained Reconfigurable Arrays. VLSI-SoC (Selected Papers) Yukio Miyasaka, Masahiro Fujita, Alan Mishchenko, John Wawrzynek
2020	A*	`conf`	SAT-Sweeping Enhanced for Logic Synthesis. DAC Luca G. Amarù, Felipe S. Marranghello, Eleonora Testa, Christopher Casares, Vinicius N. Possani, Jiong Luo, Patrick Vuillod, Alan Mishchenko, Giovanni De Micheli
2020	J	`jnl`	Simulation-Guided Boolean Resubstitution. CoRR Siang-Yun Lee, Heinz Riener, Alan Mishchenko, Robert K. Brayton, Giovanni De Micheli
2019	J	`jnl`	Circuit-Based Intrinsic Methods to Detect Overfitting. CoRR Satrajit Chatterjee, Alan Mishchenko
2019	J	`jnl`	Effective Logic Synthesis for Threshold Logic Circuit Design. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Augusto Neutzling, Jody Maick Matos, Alan Mishchenko, André Inácio Reis, Renato P. Ribas
2019	J	`jnl`	Fast Adjustable NPN Classification Using Generalized Symmetries. ACM Trans. Reconfigurable Technol. Syst. Xuegong Zhou, Lingli Wang, Alan Mishchenko
2019	—	`conf`	Logic Optimization of Majority-Inverter Graphs. MBMV Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amarù, Giovanni De Micheli, Mathias Soeken
2019	A	`conf`	On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis. DATE Heinz Riener, Winston Haaswijk, Alan Mishchenko, Giovanni De Micheli, Mathias Soeken
2019	—	`conf`	Reduction of neural network circuits by constant and nearly constant signal propagation. SBCCI Augusto Andre Souza Berndt, Alan Mishchenko, Paulo Francisco Butzen, André Inácio Reis
2019	A	`conf`	Scalable Boolean Methods in a Modern Synthesis Flow. DATE Eleonora Testa, Luca G. Amarù, Mathias Soeken, Alan Mishchenko, Patrick Vuillod, Jiong Luo, Christopher Casares, Pierre-Emmanuel Gaillardon, Giovanni De Micheli
2019	A*	`conf`	Scalable Generic Logic Synthesis: One Approach to Rule Them All. DAC Heinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca G. Amarù, Giovanni De Micheli, Mathias Soeken
2019	—	`conf`	Scaling-up ESOP Synthesis for Quantum Compilation. ISMVL Bruno Schmitt, Mathias Soeken, Giovanni De Micheli, Alan Mishchenko
2018	A*	`conf`	Canonical computation without canonical representation. DAC Alan Mishchenko, Robert K. Brayton, Ana Petkovska, Mathias Soeken, Luca G. Amarù, Antun Domic
2018	A*	`conf`	Efficient computation of ECO patch functions. DAC Ai Quoc Dao, Nian-Ze Lee, Li-Cheng Chen, Mark Po-Hung Lin, Jie-Hong R. Jiang, Alan Mishchenko, Robert K. Brayton
2018	B	`conf`	Fast Adjustable NPN Classification using Generalized Symmetries. FPL Xuegong Zhou, Lingli Wang, Peiyi Zhao, Alan Mishchenko
2018	J	`jnl`	Fast Algebraic Rewriting Based on And-Inverter Graphs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Cunxi Yu, Maciej J. Ciesielski, Alan Mishchenko
2018	A	`conf`	Improvements to boolean resynthesis. DATE Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Janet Olson, Robert K. Brayton, Giovanni De Micheli
2018	A	`conf`	Improving FPGA Performance with a S44 LUT Structure. FPGA Wenyi Feng, Jonathan W. Greene, Alan Mishchenko
2018	J	`jnl`	Pairs of majority-decomposing functions. Inf. Process. Lett. Mathias Soeken, Eleonora Testa, Alan Mishchenko, Giovanni De Micheli
2018	A	`conf`	Practical exact synthesis. DATE Mathias Soeken, Winston Haaswijk, Eleonora Testa, Alan Mishchenko, Luca Gaetano Amarù, Robert K. Brayton, Giovanni De Micheli
2018	—	`ch.`	Progressive Generation of Canonical Irredundant Sums of Products Using a SAT Solver. Advanced Logic Synthesis Ana Petkovska, Alan Mishchenko, David Novo, Muhsen Owaida, Paolo Ienne
2018	B	`conf`	Rewriting Environment for Arithmetic Circuit Verification. LPAR Cunxi Yu, Atif Yasin, Tiankai Su, Alan Mishchenko, Maciej J. Ciesielski
2018	A*	`conf`	SAT based exact synthesis using DAG topology families. DAC Winston Haaswijk, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli
2018	J	`jnl`	SAT-Based Fault Equivalence Checking in Functional Safety Verification. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Ai Quoc Dao, Mark Po-Hung Lin, Alan Mishchenko
2018	—	`conf`	SAT-based area recovery in structural technology mapping. ASP-DAC Bruno de O. Schmitt, Alan Mishchenko, Robert K. Brayton
2018	A	`conf`	Unlocking fine-grain parallelism for AIG rewriting. ICCAD Vinicius N. Possani, Yi-Shan Lu, Alan Mishchenko, Keshav Pingali, Renato P. Ribas, André Inácio Reis
2017	A	`conf`	Busy man's synthesis: Combinational delay optimization with SAT. DATE Mathias Soeken, Giovanni De Micheli, Alan Mishchenko
2017	A	`conf`	Enabling exact delay synthesis. ICCAD Luca Gaetano Amarù, Mathias Soeken, Patrick Vuillod, Jiong Luo, Alan Mishchenko, Pierre-Emmanuel Gaillardon, Janet Olson, Robert K. Brayton, Giovanni De Micheli
2017	—	`conf`	Fast-extract with cube hashing. ASP-DAC Bruno de O. Schmitt, Alan Mishchenko, Victor N. Kravets, Robert K. Brayton, André Inácio Reis
2017	B	`conf`	Property directed reachability with word-level abstraction. FMCAD Yen-Sheng Ho, Alan Mishchenko, Robert K. Brayton
2017	J	`jnl`	Reduction of Quantum Cost by Making Temporary Changes to the Function. IEICE Trans. Inf. Syst. Nurul Ain Binti Adnan, Shigeru Yamashita, Alan Mishchenko
2017	J	`jnl`	SAT solver management strategies in IC3: an experimental approach. Formal Methods Syst. Des. Gianpiero Cabodi, Paolo Camurati, Alan Mishchenko, Marco Palena, Paolo Pasini
2016	A	`conf`	2QBF: Challenges and Solutions. SAT Valeriy Balabanov, Jie-Hong Roland Jiang, Christoph Scholl, Alan Mishchenko, Robert K. Brayton
2016	—	`conf`	Clauses Versus Gates in CEGAR-Based 2QBF Solving. AAAI Workshop: Beyond NP Valeriy Balabanov, Jie-Hong Roland Jiang, Alan Mishchenko, Christoph Scholl
2016	B	`conf`	Efficient uninterpreted function abstraction and refinement for word-level model checking. FMCAD Yen-Sheng Ho, Pankaj Chauhan, Pritam Roy, Alan Mishchenko, Robert K. Brayton
2016	A	`conf`	Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications. ICCAD Ana Petkovska, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli, Robert K. Brayton, Paolo Ienne
2016	B	`conf`	Fast hierarchical NPN classification. FPL Ana Petkovska, Mathias Soeken, Giovanni De Micheli, Paolo Ienne, Alan Mishchenko
2016	A	`conf`	Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT. SAT Mathias Soeken, Alan Mishchenko, Ana Petkovska, Baruch Sterin, Paolo Ienne, Robert K. Brayton, Giovanni De Micheli
2016	J	`jnl`	m-Inductive Property of Sequential Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hamid Savoj, Alan Mishchenko, Robert K. Brayton
2015	—	`conf`	Automated Synthesis of Protocol Converters with BALM-II. SEFM Workshops Giovanni Castagnetti, Matteo Piccolo, Tiziano Villa, Nina Yevtushenko, Robert K. Brayton, Alan Mishchenko
2015	J	`jnl`	Component-Based Design by Solving Language Equations. Proc. IEEE Tiziano Villa, Alexandre Petrenko, Nina Yevtushenko, Alan Mishchenko, Robert K. Brayton
2015	—	`conf`	Exploiting Circuit Duality to Speed up SAT. ISVLSI Luca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Alan Mishchenko, Maciej J. Ciesielski, Giovanni De Micheli
2015	—	`conf`	Improved carry chain mapping for the VTR flow. FPT Ana Petkovska, Grace Zgheib, David Novo, Muhsen Owaida, Alan Mishchenko, Paolo Ienne
2015	—	`conf`	Incremental ATPG methods for multiple faults under multiple fault models. ISQED Masahiro Fujita, Naoki Taguchi, Kentaro Iwata, Alan Mishchenko
2015	A	`conf`	Technology Mapping into General Programmable Cells. FPGA Alan Mishchenko, Robert K. Brayton, Wenyi Feng, Jonathan W. Greene
2015	A	`conf`	Threshold Logic Synthesis Based on Cut Pruning. ICCAD Augusto Neutzling, Jody Maick Matos, André Inácio Reis, Renato P. Ribas, Alan Mishchenko
2014	—	`conf`	ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verification. ASP-DAC Aadithya V. Karthik, Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury
2014	A	`conf`	Constrained interpolation for guided logic synthesis. ICCAD Ana Petkovska, David Novo, Alan Mishchenko, Paolo Ienne
2014	A	`conf`	Efficient SAT-based ATPG techniques for all multiple stuck-at faults. ITC Masahiro Fujita, Alan Mishchenko
2014	C	`conf`	Logic synthesis and verification on fixed topology. VLSI-SoC Masahiro Fujita, Alan Mishchenko
2014	—	`conf`	NINJA: boolean modelling and formal verification of tiered-rate chemical reaction networks (extended abstract). BCB Aadithya V. Karthik, David Soloveichik, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury
2014	J	`jnl`	Sequential Equivalence Checking for Clock-Gated Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Hamid Savoj, Alan Mishchenko, Robert K. Brayton
2013	—	`conf`	A Fast Reparameterization Procedure. DIFTS@FMCAD Niklas Eén, Alan Mishchenko
2013	A	`conf`	A semi-canonical form for sequential AIGs. DATE Alan Mishchenko, Niklas Eén, Robert K. Brayton, Michael L. Case, Pankaj Chauhan, Nikhil Sharma
2013	A	`conf`	Core minimization in SAT-based abstraction. DATE Anton Belov, Huan Chen, Alan Mishchenko, João Marques-Silva
2013	—	`conf`	Fast Boolean matching based on NPN classification. FPT Zheng Huang, Lingli Wang, Yakov Nasikovskiy, Alan Mishchenko
2013	A	`conf`	GLA: gate-level abstraction revisited. DATE Alan Mishchenko, Niklas Eén, Robert K. Brayton, Jason Baumgartner, Hari Mony, Pradeep Kumar Nalla
2013	—	`conf`	Trading-off Incrementality and Dynamic Restart of Multiple Solvers in IC3. DIFTS@FMCAD Marco Palena, Gianpiero Cabodi, Alan Mishchenko
2012	A	`conf`	Lazy man's logic synthesis. ICCAD Wenlong Yang, Lingli Wang, Alan Mishchenko
2012	A	`conf`	Mapping into LUT structures. DATE Sayak Ray, Alan Mishchenko, Niklas Eén, Robert K. Brayton, Stephen Jang, Chao Chen
2011	A	`conf`	Delay optimization using SOP balancing. ICCAD Alan Mishchenko, Robert K. Brayton, Stephen Jang, Victor N. Kravets
2011	B	`conf`	Efficient implementation of property directed reachability. FMCAD Niklas Eén, Alan Mishchenko, Robert K. Brayton
2011	—	`conf`	Enhancing ABC for stabilization verification of SystemVerilog/VHDL models. DIFTS@FMCAD Jiang Long, Sayak Ray, Baruch Sterin, Alan Mishchenko, Robert K. Brayton
2011	J	`jnl`	Scalable don't-care-based logic optimization and resynthesis. ACM Trans. Reconfigurable Technol. Syst. Alan Mishchenko, Robert K. Brayton, Jie-Hong R. Jiang, Stephen Jang
2010	J	`jnl`	A Single-Instance Incremental SAT Formulation of Proof- and Counterexample-Based Abstraction CoRR Niklas Eén, Alan Mishchenko, Nina Amla
2010	B	`conf`	A single-instance incremental SAT formulation of proof- and counterexample-based abstraction. FMCAD Niklas Eén, Alan Mishchenko, Nina Amla
2010	A*	`conf`	ABC: An Academic Industrial-Strength Verification Tool. CAV Robert K. Brayton, Alan Mishchenko
2010	B	`conf`	Combinational techniques for sequential equivalence checking. FMCAD Hamid Savoj, David Berthelot, Alan Mishchenko, Robert K. Brayton
2010	B	`conf`	Efficient FPGA Resynthesis Using Precomputed LUT Structures. FPL Andrew A. Kennings, Alan Mishchenko, Kristofer Vorwerk, Val Pevzner, Arun Kundu
2010	A	`conf`	Global delay optimization using structural choices. FPGA Alan Mishchenko, Robert K. Brayton, Stephen Jang
2010	J	`jnl`	Logic synthesis and circuit customization using extensive external don't-cares. ACM Trans. Design Autom. Electr. Syst. Kai-Hui Chang, Valeria Bertacco, Igor L. Markov, Alan Mishchenko
2010	A	`conf`	Monolithically stackable hybrid FPGA. DATE Dmitri B. Strukov, Alan Mishchenko
2010	J	`jnl`	To SAT or Not to SAT: Scalable Exploration of Functional Dependency. IEEE Trans. Computers Jie-Hong Roland Jiang, Chih-Chun Lee, Alan Mishchenko, Chung-Yang Huang
2009	A	`conf`	Scalable don't-care-based logic optimization and resynthesis. FPGA Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Stephen Jang
2009	A	`conf`	Sequential logic synthesis using symbolic bi-decomposition. DATE Victor N. Kravets, Alan Mishchenko
2009	A	`conf`	SmartOpt: an industrial strength framework for logic synthesis. FPGA Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton
2009	A	`conf`	Speculative reduction-based scalable redundancy identification. DATE Hari Mony, Jason Baumgartner, Alan Mishchenko, Robert K. Brayton
2009	J	`jnl`	WireMap: FPGA Technology Mapping for Improved Routability and Enhanced LUT Merging. ACM Trans. Reconfigurable Technol. Syst. Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko
2008	A	`conf`	Boolean factoring and decomposition of logic networks. ICCAD Alan Mishchenko, Robert K. Brayton, Satrajit Chatterjee
2008	B	`conf`	Invariant-Strengthened Elimination of Dependent State Elements. FMCAD Michael L. Case, Alan Mishchenko, Robert K. Brayton, Jason Baumgartner, Hari Mony
2008	A*	`conf`	Merging nodes under sequential observability. DAC Michael L. Case, Victor N. Kravets, Alan Mishchenko, Robert K. Brayton
2008	B	`conf`	Recording Synthesis History for Sequential Verification. FMCAD Alan Mishchenko, Robert K. Brayton
2008	A	`conf`	Scalable and scalably-verifiable sequential synthesis. ICCAD Alan Mishchenko, Michael L. Case, Robert K. Brayton, Stephen Jang
2008	A*	`conf`	Scalable min-register retiming under timing and initializability constraints. DAC Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton
2008	A	`conf`	WireMap: FPGA technology mapping for improved routability. FPGA Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko
2007	A	`conf`	Applying Logic Synthesis for Speeding Up SAT. SAT Niklas Eén, Alan Mishchenko, Niklas Sörensson
2007	B	`conf`	Automated Extraction of Inductive Invariants to Aid Model Checking. FMCAD Michael L. Case, Alan Mishchenko, Robert K. Brayton
2007	A	`conf`	Combinational and sequential mapping with priority cuts. ICCAD Alan Mishchenko, Sungmin Cho, Satrajit Chatterjee, Robert K. Brayton
2007	J	`jnl`	Efficient Solution of Language Equations Using Partitioned Representations CoRR Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko
2007	B	`conf`	Fast Minimum-Register Retiming via Binary Maximum-Flow. FMCAD Aaron P. Hurst, Alan Mishchenko, Robert K. Brayton
2007	J	`jnl`	Improvements to Technology Mapping for LUT-Based FPGAs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
2007	A*	`conf`	On Resolution Proofs for Combinational Equivalence. DAC Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Andreas Kuehlmann
2007	J	`jnl`	SAT-Based Complete Don't-Care Computation for Network Optimization CoRR Alan Mishchenko, Robert K. Brayton
2007	A	`conf`	Scalable exploration of functional dependency by interpolation and incremental SAT solving. ICCAD Chih-Chun Lee, Jie-Hong Roland Jiang, Chung-Yang Huang, Alan Mishchenko
2006	J	`jnl`	A theory of nondeterministic networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alan Mishchenko, Robert K. Brayton
2006	A*	`conf`	DAG-aware AIG rewriting a fresh look at combinational logic synthesis. DAC Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
2006	A	`conf`	Factor cuts. ICCAD Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton
2006	A	`conf`	Improvements to combinational equivalence checking. ICCAD Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton, Niklas Eén
2006	A	`conf`	Improvements to technology mapping for LUT-based FPGAs. FPGA Alan Mishchenko, Satrajit Chatterjee, Robert K. Brayton
2006	J	`jnl`	Linear cofactor relationships in Boolean functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch
2006	J	`jnl`	Reducing Structural Bias in Technology Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam
2006	A*	`conf`	Symmetry detection for large Boolean functions using circuit representation, simulation, and satisfiability. DAC Jin S. Zhang, Alan Mishchenko, Robert K. Brayton, Malgorzata Chrzanowska-Jeske
2006	J	`jnl`	Using simulation and satisfiability to compute flexibilities in Boolean networks. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alan Mishchenko, Jin S. Zhang, Subarnarekha Sinha, Jerry R. Burch, Robert K. Brayton, Malgorzata Chrzanowska-Jeske
2005	—	`conf`	Detecting support-reducing bound sets using two-cofactor symmetries. ASP-DAC Jin S. Zhang, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Jerry R. Burch
2005	A	`conf`	Efficient Solution of Language Equations Using Partitioned Representations. DATE Alan Mishchenko, Robert K. Brayton, Jie-Hong Roland Jiang, Tiziano Villa, Nina Yevtushenko
2005	J	`jnl`	Exact and Heuristic Minimization of the Average Path Length in Decision Diagrams. J. Multiple Valued Log. Soft Comput. Shinobu Nagayama, Alan Mishchenko, Tsutomu Sasao, Jon T. Butler
2005	A	`conf`	Reducing structural bias in technology mapping. ICCAD Satrajit Chatterjee, Alan Mishchenko, Robert K. Brayton, Xinning Wang, Timothy Kam
2005	A	`conf`	SAT-Based Complete Don't-Care Computation for Network Optimization. DATE Alan Mishchenko, Robert K. Brayton
2005	—	`conf`	Synthesis for regularity using decision diagrams [logic IC synthesis and layout]. ISCAS (5) Malgorzata Chrzanowska-Jeske, Alan Mishchenko
2004	A	`conf`	On breakable cyclic definitions. ICCAD Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton
2003	A	`conf`	A Theory of Non-Deterministic Networks. ICCAD Alan Mishchenko, Robert K. Brayton
2003	A*	`conf`	A new enhanced constructive decomposition and mapping algorithm. DAC Alan Mishchenko, Xinning Wang, Timothy Kam
2003	J	`jnl`	Board-level multiterminal net assignment for the partial cross-bar architecture. IEEE Trans. Very Large Scale Integr. Syst. Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Andrew A. Kennings, Alan J. Coppola
2003	J	`jnl`	Fast computation of symmetries in Boolean functions. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Alan Mishchenko
2003	A*	`conf`	Large-scale SOP minimization using decomposition and functional properties. DAC Alan Mishchenko, Tsutomu Sasao
2003	A	`conf`	Reducing Multi-Valued Algebraic Operations to Binary. DATE Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton
2002	—	`conf`	A Boolean Paradigm in Multi-Valued Logic Synthesis. IWLS Alan Mishchenko, Robert K. Brayton
2002	—	`conf`	Board-level multiterminal net assignment. ACM Great Lakes Symposium on VLSI Xiaoyu Song, William N. N. Hung, Alan Mishchenko, Malgorzata Chrzanowska-Jeske, Alan J. Coppola, Andrew A. Kennings
2002	—	`conf`	Encoding of Boolean Functions and its Application to LUT Cascade Synthesis. IWLS Alan Mishchenko, Tsutomu Sasao
2002	J	`jnl`	Generalized Inclusive Forms - New Canonical Reed-Muller Forms Including Minimum ESOPs. VLSI Design Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Marek A. Perkowski
2002	—	`conf`	Logic Synthesis of Reversible Wave Cascades. IWLS Alan Mishchenko, Marek A. Perkowski
2002	—	`conf`	Optimization of Multi-Valued Multi-Level Networks. ISMVL Robert K. Brayton, M. Gao, Jie-Hong Roland Jiang, Yunjian Jiang, Yinghua Li, Alan Mishchenko, Subarnarekha Sinha, Tiziano Villa
2002	—	`conf`	Reducing Multi-Valued Algebraic Operations to Binary. IWLS Jie-Hong Roland Jiang, Alan Mishchenko, Robert K. Brayton
2002	—	`conf`	Simplification of Non-Deterministic Multi-Valued Networks. IWLS Alan Mishchenko, Robert K. Brayton
2002	A	`conf`	Simplification of non-deterministic multi-valued networks. ICCAD Alan Mishchenko, Robert K. Brayton
2002	—	`conf`	Topologically Constrained Logic Synthesis. IWLS Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton
2002	A	`conf`	Topologically constrained logic synthesis. ICCAD Subarnarekha Sinha, Alan Mishchenko, Robert K. Brayton
2001	A*	`conf`	An Algorithm for Bi-Decomposition of Logic Functions. DAC Alan Mishchenko, Bernd Steinbach, Marek A. Perkowski
2001	C	`conf`	Regular Realization of Symmetric Functions Using Reversible Logic. DSD Marek A. Perkowski, Malgorzata Chrzanowska-Jeske, Alan Mishchenko, Xiaoyu Song, Anas Al-Rabadi, Bart Massey, Pawel Kerntopf, Andrzej Buller, Lech Józwiak, Alan J. Coppola
1999	—	`conf`	Evolvable Hardware or Learning Hardware? Induction of State Machines from Temporal Logic Constraints. Evolvable Hardware Marek A. Perkowski, Alan Mishchenko, Anatoli N. Chebotarev
1999	A*	`conf`	Graph Coloring Algorithms for Fast Evaluation of Curtis Decompositions. DAC Marek A. Perkowski, Rahul Malvi, Stan Grygiel, Michael Burns, Alan Mishchenko