Alak Majumder - RankMe

47 papers Misc 1Journal 25Unranked 21

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	An Approach of ISI Elimination and High-Speed Data Reconstruction in Lossy On-Chip Serial Link. Circuits Syst. Signal Process. Anirban Tarafdar, Alak Majumder, Biman Debbarma, Bidyut K. Bhattacharyya
2026	J	`jnl`	Dynamic Header Switch to Influence Switching Current Profile of an IC Chip. Circuits Syst. Signal Process. Vijay Pratap Yadav, Vipin Kumar Singh, Ashish Ranjan Kumar, Tika Ram Pokhrel, Sanjeev Kumar Metya, Alak Majumder
2026	J	`jnl`	Work Function Tuning in Strain Induced Double Gated Junctionless Transistor: A Device to Circuit Performance Study for Sub-20nm Nodes. Circuits Syst. Signal Process. Tika Ram Pokhrel, Alaaddin Al-Shidaifat, Hanjung Song, Alak Majumder
2025	—	`conf`	A Multi-Resolution Mode Energy and Area Efficient All Digital Smart Temperature Sensor. ICEIC Kuntal Chakraborty, Alak Majumder, Abir J. Mondal
2025	J	`jnl`	Multi-mode Power Gating to Reduce Current Ramp of Logic Circuit. Circuits Syst. Signal Process. Vijay Pratap Yadav, Vipin Kumar Singh, Sanjeev Kumar Metya, Alak Majumder
2025	—	`conf`	Soft-Start Header Power Gating for Inrush Alleviated Current Profile. ICEIC Vijay Pratap Yadav, Vipin Kumar Singh, Tika Ram Pokhrel, Abir Jyoti Mandal, Sanjeev Kumar Metya, Alak Majumder
2024	—	`conf`	A Method of Variable Frequency Clock Generation. iSES Vipin Kumar Singh, Vijay Pratap Yadav, Tika Ram Pokhrel, Pritam Bhattacharjee, Alak Majumder
2024	—	`conf`	An Algorithmic Approach of Generating a VFC of Low Average Frequency Ramp. iSES Priyanka J, Ankita Deb, Pritam Bhattacharjee, Alak Majumder
2024	Misc	`conf`	Design of VFC with Programmable Frequency Ramp to control on-chip switching current profile. VLSID Pritam Bhattacharjee, Alak Majumder
2024	—	`conf`	Design of an Operational Transconductance Amplifier-Based Charge Pump for Phase-Locked Loop Applications. iSES Payali Das, Alak Majumder
2024	J	`jnl`	Enhancing intrusion detection using wireless sensor networks: A novel ahp-madm aggregated multiple type 3 fuzzy logic-based k-barriers prediction system. Peer Peer Netw. Appl. Anirban Tarafdar, Azharuddin Sheikh, Pinki Majumder, Abhijit Baidya, Alak Majumder, Bidyut K. Bhattacharyya, Uttam Kumar Bera
2024	—	`conf`	Exploring the Application of Variable Frequency Clock as the Constituent of OCT. iSES Priyanka J, Pritam Bhattacharjee, Alak Majumder
2024	J	`jnl`	Time Domain and Area Efficient Smart Temperature Sensor Exploiting Channel Length Modulation Coefficient. J. Circuits Syst. Comput. Kuntal Chakraborty, Alak Majumder, Abir J. Mondal
2023	J	`jnl`	A variation resilient keeper design for high performance domino logic applications. Integr. Jyoti Kandpal, Tika Ram Pokhrel, Shalu Saini, Alak Majumder
2023	—	`conf`	Comparative Exploration of Gate Count and Leakage Optimized D-Latch in Nanometer CMOS. RADIOELEKTRONIKA Pritam Bhattacharjee, G. Naveen Goud, Vipin Kumar Singh, Vijay Pratap Yadav, Abir J. Mondal, Alak Majumder
2023	—	`conf`	Double Gate JLT Based New TIGFET for Dynamic C APCCAS Tika Ram Pokhrel, Alak Majumder
2023	—	`conf`	Ti:LiNbO3 Based EO-MZI Count Optimized Design of Reversible Peres Gate. RADIOELEKTRONIKA Barnali Chowdhury, Shashank Awasthi, Mohammad Arif Bin Jalil, Alak Majumder, Sanjeev Kumar Metya
2022	J	`jnl`	A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link. Integr. Mithilesh Kumar, Alak Majumder, Abir J. Mondal, Arijit Raychowdhury, Bidyut K. Bhattacharyya
2022	J	`jnl`	Clock-Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Pritam Bhattacharjee, Prerna Rana, Bidyut K. Bhattacharyya, Alak Majumder
2022	J	`jnl`	Simulation and Analysis of a Digitally Controlled Differential Delay Circuit Under Process, Voltage, Temperature and Noise Due to Injection of High Current. J. Circuits Syst. Comput. Mithilesh Kumar, Alak Majumder, Abir J. Mondal
2021	J	`jnl`	A Vector-Controlled Variable Delay Circuit to Develop Near-Symmetric Output Rise/Fall Time. Circuits Syst. Signal Process. Pritam Bhattacharjee, Bidyut K. Bhattacharyya, Alak Majumder
2020	—	`conf`	A 90nm PVT Tolerant Current Mode Frequency Divider with Wide Locking Range. NorCAS Madhusudan Maiti, Shubhro Chakrabartty, Alaaddin Al-Shidaifat, Hanjung Song, Bidyut K. Bhattacharyya, Alak Majumder
2020	—	`conf`	Electro-optic Reversible Toffoli Gate with Optimal Count of LiNbO3 Mach-Zehnder Interferometers. NorCAS Shashank Awasthi, Saurav Sharma, Sanjeev Kumar Metya, Alak Majumder
2020	J	`jnl`	Modelling and analysis of a hybrid CS-CMOS ring VCO with wide tuning range. Microelectron. J. Madhusudan Maiti, Alak Majumder, Shubhro Chakrabartty, Hanjung Song, Bidyut K. Bhattacharyya
2019	J	`jnl`	A Variation-Aware Robust Gated Flip-Flop for Power-Constrained FSM Application. J. Circuits Syst. Comput. Pritam Bhattacharjee, Alak Majumder
2019	J	`jnl`	Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication. IEEE Trans. Circuits Syst. I Regul. Pap. Alak Majumder, Monalisa Das, Suraj Kumar Saw, Abir J. Mondal, Bidyut K. Bhattacharyya
2018	J	`jnl`	A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%. J. Circuits Syst. Comput. Nivedita Laskar, Suman Debnath, Alak Majumder, Bidyut K. Bhattacharyya
2018	J	`jnl`	A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chips. J. Circuits Syst. Comput. Alak Majumder, Pritam Bhattacharjee, Tushar Dhabal Das
2018	J	`jnl`	Data-Dependent Clock Gating approach for Low Power Sequential System. CoRR Dhiraj Sarkar, Pritam Bhattacharjee, Alak Majumder
2018	J	`jnl`	LECTOR Based Clock Gating for Low Power Multi-Stage Flip Flop Applications. CoRR Pritam Bhattacharjee, Bipasha Nath, Alak Majumder
2017	J	`jnl`	A 65 nm Design of 0.6 V/8.98 J. Low Power Electron. Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya
2017	—	`conf`	A 90nm Novel MUX-Dual Latch Design Approach for Gigascale Serializer Application. iNIS Monalisa Das, Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya
2017	—	`conf`	A Design Methodology for MOS Current Mode Logic VCO. iNIS Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya
2017	J	`jnl`	A mathematical formulation to design and implementation of a low voltage swing transceiver circuit. Integr. Abir J. Mondal, Alak Majumder, Bidyut K. Bhattacharyya
2017	—	`conf`	Binary Counter Based Gated Clock Tree for Integrated CPU Chip. iNIS Bipasha Nath, Alak Majumder
2017	—	`conf`	Current Profile Generated by Gating Logic Reduces Power Supply Noise of Integrated CPU Chip. iNIS Alak Majumder, Pritam Bhattacharjee
2017	J	`jnl`	Gated Clock Tree Circuit to Reduce the Noise in Silicon Chip. J. Low Power Electron. Alak Majumder
2017	J	`jnl`	Pay-Cloak: A Biometric Back Cover for Smartphones: Facilitating secure contactless payments and identity virtualization at low cost to end users. IEEE Consumer Electron. Mag. Alak Majumder, Joyeeta Goswami, Shirsha Ghosh, Rishu Shrivastawa, Saraju P. Mohanty, Bidyut K. Bhattacharyya
2017	J	`jnl`	Reconstruction of a single square pulse originally having 40 ps width coming from a lossy and noisy channel in a point to point interconnect. Turkish J. Electr. Eng. Comput. Sci. Alak Majumder, Bidyut K. Bhattacharyya
2017	J	`jnl`	Swing-Pay: One Card Meets All User Payment and Identity Needs: A Digital Card Module using NFC and Biometric Authentication for Peer-to-Peer Payment. IEEE Consumer Electron. Mag. Shirsha Ghosh, Alak Majumder, Joyeeta Goswami, Abhishek Kumar, Saraju P. Mohanty, Bidyut K. Bhattacharyya
2017	J	`jnl`	Threshold adjustment of receiver chip to achieve a data rate >66 Gbit/sec in point to point interconnect. Integr. Alak Majumder, Abir J. Mondal, Bidyut K. Bhattacharyya
2016	—	`conf`	A 90 nm leakage control transistor based clock gating for low power flip flop applications. MWSCAS Pritam Bhattacharjee, Alak Majumder, Tushar Dhabal Das
2016	—	`conf`	A constraint driven technique for MOS amplifier design. VDAT Paromita Bhattacharjee, Abir J. Mondal, Alak Majumder
2016	—	`conf`	A method to design a comparator for sampled data processing applications. VDAT Rama Prasad Acharya, Abir J. Mondal, Alak Majumder
2016	—	`conf`	LECTOR Based Gated Clock Approach to Design Low Power FSM for Serial Adder. iNIS Pritam Bhattacharjee, Alak Majumder
2015	—	`conf`	Development of a prototype to detect speed limit violation for better traffic management. IC3 Joyeeta Goswami, Shirsha Ghosh, Shivaditya Katiyar, Alak Majumder
2015	—	`conf`	Generation and performance evaluation of reconfigurable random routing algorithm for 2D-mesh NoCs. LATS Sandeep Kumar Singh, Abir J. Mondal, Alak Majumder