Akira Tsuchiya

85 papers C 3Journal 25Unranked 57

Year	Rank	Type	Title / Venue / Authors
2024	J	`jnl`	A 16-Channel Optical Receiver Circuit for a Multicore Fiber-Based Co-Packaged Optics Module in a 65-nm CMOS Chip. IEEE Trans. Circuits Syst. II Express Briefs Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura
2024	—	`conf`	A 25-Gb/s Active Feedback Transimpedance Amplifier in 65-nm CMOS. ICEIC Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine
2024	—	`conf`	A Small-Area and Low-EPB Inductive-Peaking VCSEL Driver for a 65-nm CMOS Chip. SOCC Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
2024	J	`jnl`	A burst-mode receiver with quick response and high consecutive identical digit tolerance for advanced intra-vehicle optical networks. Microelectron. J. Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
2023	J	`jnl`	10Gb/s burst-mode driver circuit with on-chip bias switch for in-Vehicle optical networks. IEICE Electron. Express Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2023	—	`conf`	4-ch 25-Gb/s Small and Low-power VCSEL Driver Circuit with Unbalanced CML in 65-nm CMOS. ISOCC Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2023	—	`conf`	A 4×32-Gb/s VCSEL Driver with Adaptive Feedforward Equalization in 65-nm CMOS. ICECS Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
2023	—	`conf`	High-Speed, Low-Power, and Small-Area Optical Receiver in 65-nm CMOS. ASICON Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
2023	J	`jnl`	Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process. IEICE Electron. Express Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine
2022	—	`conf`	A 28-Gb/s VCSEL Driver with Variable Output Impedance in 65-nm CMOS. MWSCAS Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
2022	—	`conf`	A Burst-Mode TIA with Automatic Power Saving and DC Wander Reduction in 65-nm CMOS. ICECS 2022 Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
2022	—	`conf`	A Fine-Tuning Phase Shifter with Vector Synthesizer Using 65-nm CMOS for Beamforming in 24-GHz Band. ICECS 2022 Masataka Inoue, Shinya Nakashioya, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2022	—	`conf`	A Method for Implementing LSTM-Based Multiple-People Identification System for Non-Contact Health Monitoring on Small-Scale FPGA. ISOCC Masanao Okamoto, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2022	—	`conf`	A Small-Area Integration of Optical Receiver Using Multi-Layer Inductors and Capacitor-Under-Pad. MWSCAS Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura
2022	—	`conf`	A preamplifier circuit with offset-voltage control technique for 50-Gb/s CMOS PAM4 receiver. ICEIC Masaya Miyabe, Toshiyuki Inoue, Masataka Inoue, Shinya Nakashioya, Akira Tsuchiya, Keiji Kishine
2022	—	`conf`	Capacitor Under Pad for Small Area Integration of High-Speed Signal-to-Differential Amplifier. ICEIC Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine, Yasuhiro Takahashi, Daisuke Ito, Makoto Nakamura
2022	—	`conf`	Memory-Access Optimization for Acceleration and Power Saving of FPGA-Based Image Processing. ISOCC Shungo Shimohane, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2022	—	`conf`	Method of Estimating Positions for Multiple People in Non-Contact Vital Signs Monitoring Systems. ICEIC Masaya Kashiwagi, Toshiyuki Inoue, Masanao Okamoto, Akira Tsuchiya, Keiji Kishine
2022	—	`conf`	Process Acceleration for HEVC Using Parallel Characteristics Calculation and Pixel Array Conversion. ICEIC Rei Yamazaki, Toshiyuki Inoue, Yuuki Teramura, Akira Tsuchiya, Keiji Kishine
2022	—	`conf`	Smart Computational Resource Distribution System with Automatic Classification Interface for CPS. ISOCC Yuuki Teramura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2022	—	`conf`	Supply-Variation-Tolerant Transimpedance Amplifier Using Non-Inverting Amplifier in 180-nm CMOS. ASP-DAC Tomofumi Tsuchida, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine
2021	—	`conf`	5-Gb/s PAM4 Transmitter IC Using Compensation Circuit in an 180-nm CMOS. ICEIC Yudai Ichii, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2021	—	`conf`	A Burst-Mode TIA with Adaptive Response and Stable Operation for in-Vehicle Optical Networks. ICECS Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Daisuke Ito, Yasuhiro Takahashi, Makoto Nakamura
2021	—	`conf`	Implementation of Low-Energy LSTM with Parallel and Pipelined Algorithm in Small-Scale FPGA. ICEIC Ukyo Yoshimura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2021	—	`conf`	Supply Noise Reduction Filter for Parallel Integrated Transimpedance Amplifiers. ASP-DAC Shinya Tanimura, Akira Tsuchiya, Toshiyuki Inoue, Keiji Kishine
2020	J	`jnl`	Design of a 45 Gb/s, 98 fJ/bit, 0.02 mm IEICE Trans. Electron. Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera
2020	—	`conf`	Processing Time Reduction for JPEG Compression Using Pixel Array Conversion. ISOCC Rei Yamazaki, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2019	—	`conf`	A 45 Gb/s, 98 fJ/bit, 0.02 mm SoCC Akira Tsuchiya, Akitaka Hiratsuka, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera
2019	—	`conf`	Design of Crosstalk Noise Filter for Multi-Channel Transimpedance Amplifier. SoCC Shinya Tanimura, Akira Tsuchiya, Ryosuke Noguchi, Toshiyuki Inoue, Keiji Kishine
2019	—	`conf`	Frequency Discriminator Using a Simple AD Converter for Interface Systems. ISOCC Sanshiro Kimura, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2019	J	`jnl`	Impact of On-Chip Inductor and Power-Delivery-Network Stacking on Signal and Power Integrity. IEICE Trans. Electron. Akira Tsuchiya, Akitaka Hiratsuka, Toshiyuki Inoue, Keiji Kishine, Hidetoshi Onodera
2019	—	`conf`	Optimization Technique of Memory Traffic for FPGA-Based Image Processing System. ISOCC Kenta Nishiguchi, Toshiyuki Inoue, Akira Tsuchiya, Kazunori Ogohara, Keiji Kishine
2019	—	`conf`	Suitable-Compensation Circuit Design for a PAM4 Transmitter in 180-nm CMOS. ISOCC Yudai Ichii, Ryosuke Noguchi, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2018	—	`conf`	A 25-Gb/s 13 mW clock and data recovery using C VLSI-DAT Ryosuke Noguchi, Kosuke Furuichi, Hiromu Uemura, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Hiroaki Katsurai, Shinsuke Nakano, Hideyuki Nosaka
2018	—	`conf`	A 25-Gb/s Low-Power Clock and Data Recovery with an Active-Stabilizing CML-CMOS Conversion. ICECS Ryosuke Noguchi, Atsuto Imajo, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2018	—	`conf`	A Low Input Referred Noise and Low Crosstalk Noise 25 Gb/s Transimpedance Amplifier with Inductor-Less Bandwidth Compensation. A-SSCC Akitaka Hiratsuka, Akira Tsuchiya, Kenji Tanaka, Hiroyuki Fukuyama, Naoki Miura, Hideyuki Nosaka, Hidetoshi Onodera
2018	—	`conf`	Low-Power and High-Linearity Inductorless Low-Noise Amplifiers with Active-Shunt-Feedback in 65-nm CMOS Technology. MWSCAS Toshiyuki Inoue, Ryosuke Noguchi, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2017	—	`conf`	Compact implementation IIR filter in FPGA for noise reduction of sensor signal. ISOCC Koki Arauchi, Shohei Maki, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2017	—	`conf`	Design method for inductorless low-noise amplifiers with active shunt-feedback in 65-nm CMOS. ISOCC Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine, Makoto Nakamura
2017	—	`conf`	FPGA-based transceiver circuit for labeling signal transmission system. ISOCC Kohei Nomura, Natsuyuki Koda, Toshiyuki Inoue, Akira Tsuchiya, Keiji Kishine
2017	—	`conf`	Power-bandwidth trade-off analysis of multi-stage inverter-type transimpedance amplifier for optical communication. MWSCAS Akitaka Hiratsuka, Akira Tsuchiya, Hidetoshi Onodera
2016	—	`conf`	36-Gb/s CDR IC using simple passive loop filter combined with passive load in phase detector. ISOCC Keiji Kishine, Hiroshi Inoue, Kosuke Furuichi, Natsuyuki Koda, Hiromu Uemura, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya
2015	—	`conf`	A 25-Gb/s 480-mW CMOS modulator driver using area-efficient 3D inductor peaking. A-SSCC Shinsuke Nakano, Masafumi Nogawa, Hideyuki Nosaka, Akira Tsuchiya, Hidetoshi Onodera, Shunji Kimura
2015	J	`jnl`	A Forward/Reverse Body Bias Generator with Wide Supply-Range down to Threshold Voltage. IEICE Trans. Electron. Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera
2015	J	`jnl`	A Multi-Rate Burst-Mode CDR Using a GVCO With Symmetric Loops for Instantaneous Phase Locking in 65-nm CMOS. IEEE Trans. Circuits Syst. I Regul. Pap. Keiji Kishine, Hiromi Inaba, Hiroshi Inoue, Makoto Nakamura, Akira Tsuchiya, Hiroaki Katsurai, Hidetoshi Onodera
2015	—	`conf`	Energy reduction by built-in body biasing with single supply voltage operation. ISQED Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Tohru Ishihara, Hidetoshi Onodera
2014	C	`conf`	A 65-nm CMOS burst-mode CDR based on a GVCO with symmetric loops. ISCAS Keiji Kishine, Hiroshi Inoue, Hiromi Inaba, Makoto Nakamura, Akira Tsuchiya, Hidetoshi Onodera, Hiroaki Katsurai
2014	J	`jnl`	A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera
2014	—	`conf`	A body bias generator with wide supply-range down to threshold voltage for within-die variability compensation. A-SSCC Norihiro Kamae, Islam A. K. M. Mahfuzul, Akira Tsuchiya, Hidetoshi Onodera
2014	J	`jnl`	Analysis of Radiation-Induced Clock-Perturbation in Phase-Locked Loop. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Sinnyoung Kim, Akira Tsuchiya, Hidetoshi Onodera
2014	J	`jnl`	Radiation-Hardened PLL with a Switchable Dual Modular Redundancy Structure. IEICE Trans. Electron. Sinnyoung Kim, Akira Tsuchiya, Hidetoshi Onodera
2013	—	`conf`	A 25-Gb/s LD driver with area-effective inductor in a 0.18-µm CMOS. ASP-DAC Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2013	C	`conf`	Perturbation-immune radiation-hardened PLL with a switchable DMR structure. IOLTS Sinnyoung Kim, Akira Tsuchiya, Hidetoshi Onodera
2012	—	`conf`	A 16Gb/s area-efficient LD driver with interwoven inductor in a 0.18µm CMOS. ASP-DAC Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2012	J	`jnl`	Area-Effective Inductive Peaking with Interwoven Inductor for High-Speed Laser-Diode Driver for Optical Communication System. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2011	—	`conf`	A 10.3Gbps translmpedance amplifier with mutually coupled inductors in 0.18-μm CMOS. ISOCC Shigekazu Miyawaki, Makoto Nakamura, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2011	—	`conf`	An area effective forward/reverse body bias generator for within-die variability compensation. A-SSCC Norihiro Kamae, Akira Tsuchiya, Hidetoshi Onodera
2011	—	`conf`	Bandwidth enhancement for high speed amplifier utilizing mutually coupled on-chip inductors. ISOCC Akira Tsuchiya, Takeshi Kuboki, Yusuke Ohtomo, Keiji Kishine, Shigekazu Miyawaki, Makoto Nakamura, Hidetoshi Onodera
2010	—	`conf`	A 16Gbps laser-diode driver with interwoven peaking inductors in 0.18-µm CMOS. CICC Takeshi Kuboki, Yusuke Ohtomo, Akira Tsuchiya, Keiji Kishine, Hidetoshi Onodera
2010	—	`conf`	A design procedure of predictive RF MOSFET model for compatibility with ITRS. SoCC Sinnyoung Kim, Akira Tsuchiya, Hidetoshi Onodera
2010	J	`jnl`	Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells. Inf. Media Technol. Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
2010	J	`jnl`	Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells. IPSJ Trans. Syst. LSI Des. Methodol. Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
2009	—	`conf`	Erect of regularity-enhanced layout on printability and circuit performance of standard cells. ISQED Hiroki Sunagawa, Haruhiko Terada, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
2009	—	`conf`	High performance on-chip differential signaling using passive compensation for global communication. ASP-DAC Ling Zhang, Yulei Zhang, Akira Tsuchiya, Masanori Hashimoto, Ernest S. Kuh, Chung-Kuan Cheng
2009	J	`jnl`	Statistical Gate Delay Model for Multiple Input Switching. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
2008	J	`jnl`	Accurate Estimation of the Worst-case Delay in Statistical Static Timing Analysis. Inf. Media Technol. Haruhiko Terada, Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
2008	J	`jnl`	Accurate Estimation of the Worst-case Delay in Statistical Static Timing Analysis. IPSJ Trans. Syst. LSI Des. Methodol. Haruhiko Terada, Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
2008	J	`jnl`	Analytical Eye-Diagram Model for On-Chip Distortionless Transmission Lines and Its Application to Design Space Exploration. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng
2008	C	`conf`	On-chip high performance signaling using passive compensation. ICCD Yulei Zhang, Ling Zhang, Akira Tsuchiya, Masanori Hashimoto, Chung-Kuan Cheng
2008	—	`conf`	Statistical gate delay model for Multiple Input Switching. ASP-DAC Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
2007	—	`conf`	A 10Gbps/channel On-Chip Signaling Circuit with an Impedance-Unmatched CML Driver in 90nm CMOS Technology. ASP-DAC Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera
2007	—	`conf`	Analytical Eye-diagram Model for On-chip Distortionless Transmission Lines and Its Application to Design Space Exploration. CICC Masanori Hashimoto, Jangsombatsiri Siriporn, Akira Tsuchiya, Haikun Zhu, Chung-Kuan Cheng
2007	J	`jnl`	Low-Power Design of CML Driver for On-Chip Transmission-Lines Using Impedance-Unmatched Driver. IEICE Trans. Electron. Takeshi Kuboki, Akira Tsuchiya, Hidetoshi Onodera
2007	J	`jnl`	Optimal Termination of On-Chip Transmission-Lines for High-Speed Signaling. IEICE Trans. Electron. Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2007	—	`conf`	Worst-case delay analysis considering the variability of transistors and interconnects. ISPD Takayuki Fukuoka, Akira Tsuchiya, Hidetoshi Onodera
2006	J	`jnl`	Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect. IEICE Trans. Electron. Yoichi Yuyama, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera
2006	J	`jnl`	Interconnect RL Extraction Based on Transfer Characteristics of Transmission-Line. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2006	—	`conf`	Interconnect RL extraction at a single representative frequency. ASP-DAC Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2006	J	`jnl`	Si-Substrate Modeling toward Substrate-Aware Interconnect Resistance and Inductance Extraction in SoC Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Toshiki Kanamoto, Tatsuhiko Ikeda, Akira Tsuchiya, Hidetoshi Onodera, Masanori Hashimoto
2005	—	`conf`	Design guideline for resistive termination of on-chip high-speed interconnects. CICC Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2005	J	`jnl`	Performance Limitation of On-Chip Global Interconnects for High-Speed Signaling. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2005	—	`conf`	Return path selection for loop RL extraction. ASP-DAC Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2004	—	`conf`	Performance limitation of on-chip global interconnects for high-speed signaling. CICC Akira Tsuchiya, Yuuya Gotoh, Masanori Hashimoto, Hidetoshi Onodera
2004	—	`conf`	Representative frequency for interconnect R(f)L(f)C extraction. ASP-DAC Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera
2003	J	`jnl`	Representative Frequency for Interconnect R(f)L(f)C Extraction. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera