Akira Tamakoshi

13 papers C 1Journal 5Unranked 7
YearRankTypeTitle / Venue / Authors
2025 — conf
An FPGA-based rapid-prototyping platform for spintronics-based edge-computing hardware.
ISMVL
Daisuke Suzuki, Akira Tamakoshi, Tomohiro Yoneda, Masanori Natsui, Yasuhiro Takako, Takahiro Hanyu
2025 — conf
Implementation of an MRAM-Based Edge AI Hardware with a Fine-Grained Power-Gating Technique.
ISMVL
Tomohiro Yoneda, Yasuhiro Takako, Akira Tamakoshi, Masanori Natsui, Daisuke Suzuki, Takahiro Hanyu
2021 J jnl
Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition.
IEEE J. Solid State Circuits
Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2021 J jnl
Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices.
IEEE Open J. Circuits Syst.
Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu
2021 — conf
Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices.
SiPS
Naoya Onizawa, Akira Tamakoshi, Takahiro Hanyu
2020 — conf
Design of an Energy-Efficient True Random Number Generator Based on Triple Read-Write Data-Stream Multiplexing of MTJ Devices.
NEWCAS
Akira Tamakoshi, Naoya Onizawa, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
2020 — conf
Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage.
VLSI Circuits
Masanori Natsui, Akira Tamakoshi, Hiroaki Honjo, Toshinari Watanabe, Takashi Nasuno, Chaoliang Zhang, Takaho Tanigawa, Hirofumi Inoue, Masaaki Niwa, Toru Yoshiduka, Yasuo Noguchi, Mitsuo Yasuhira, Yitao Ma, Hui Shen, Shunsuke Fukami, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2020 J jnl
High-Throughput/Low-Energy MTJ-Based True Random Number Generator Using a Multi-Voltage/Current Converter.
IEEE Trans. Very Large Scale Integr. Syst.
Naoya Onizawa, Shogo Mukaida, Akira Tamakoshi, Hitoshi Yamagata, Hiroyuki Fujita, Takahiro Hanyu
2019 J jnl
A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications.
IEEE J. Solid State Circuits
Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2019 — conf
An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz.
ISSCC
Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2017 J jnl
Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors.
IEEE Trans. Emerg. Top. Comput.
Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu
2016 C conf
Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design.
ISCAS
Masanori Natsui, Akira Tamakoshi, Akira Mochizuki, Hiroki Koike, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu
2015 — conf
A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery.
NANOARCH
Naoya Onizawa, Akira Mochizuki, Akira Tamakoshi, Takahiro Hanyu