Akira Nishida

15 papers A 1C 2Misc 2Journal 2Unranked 7
YearRankTypeTitle / Venue / Authors
2011 — conf
Parareal Acceleration of Matrix Multiplication.
PARCO
Toshiya Takami, Akira Nishida
2010 — conf
Experience in Developing an Open Source Scalable Software Infrastructure in Japan.
ICCSA (2)
Akira Nishida
2010 — ch.
Toward Automatic Performance Tuning for Numerical Simulations in the SILC Matrix Computation Framework.
Software Automatic Tuning, From Concepts to State-of-the-Art Results
Tamito Kajiyama, Akira Nukada, Reiji Suda, Hidehiko Hasegawa, Akira Nishida
2007 Misc conf
Cloth Simulation in the SILC Matrix Computation Framework: A Case Study.
PPAM
Tamito Kajiyama, Akira Nukada, Reiji Suda, Hidehiko Hasegawa, Akira Nishida
2007 C conf
High Performance 3D Convolution for Protein Docking on IBM Blue Gene.
ISPA
Akira Nukada, Yuichiro Hourai, Akira Nishida, Yutaka Akiyama
2007 C conf
High Performance FFT on SGI Altix 3700.
HPCC
Akira Nukada, Daisuke Takahashi, Reiji Suda, Akira Nishida
2006 — conf
Building Cost Effective High Performance Computing Environment via PCI Express.
ICPP Workshops
Akira Nishida
2006 — conf
Distributed SILC: An Easy-to-Use Interface for MPI-Based Parallel Matrix Computation Libraries.
PARA
Tamito Kajiyama, Akira Nukada, Reiji Suda, Hidehiko Hasegawa, Akira Nishida
2006 A conf
Poster reception - Scalable software infrastructure project.
SC
Akira Nishida, Hisashi Kotakemori, Tamito Kajiyama, Akira Nukada
2005 — conf
Network-aware Data mMapping on Parallel Molecular Dynamicas.
ICPADS (1)
Yuichiro Hourai, Akira Nishida, Yoshio Oyanagi
2005 — conf
Performance Evaluation of Parallel Sparse Matrix-Vector Products on SGI Altix3700.
IWOMP
Hisashi Kotakemori, Hidehiko Hasegawa, Tamito Kajiyama, Akira Nukada, Reiji Suda, Akira Nishida
2005 Misc conf
SILC: A Flexible and Environment-Independent Interface for Matrix Computation Libraries.
PPAM
Tamito Kajiyama, Akira Nukada, Hidehiko Hasegawa, Reiji Suda, Akira Nishida
2003 — conf
Performance Evaluation of Low Level Multithreaded BLAS Kernels on Intel Processor Based cc-NUMA Systems.
ISHPC
Akira Nishida, Yoshio Oyanagi
1999 J jnl
110-GB/s simultaneous bidirectional transceiver logic synchronized with a system clock.
IEEE J. Solid State Circuits
Toshiro Takahashi, Takashi Muto, Yuji Shirai, Fumihiko Shirotori, Yoshifumi Takada, Akira Yamagiwa, Akira Nishida, Atsuo Hotta, Tadashi Kiyuna
1999 J jnl
A high performance parallelization scheme for the Hessenberg double shift QR algorithm.
Parallel Comput.
Reiji Suda, Akira Nishida, Yoshio Oyanagi