Akira Nagoya - RankMe

32 papers A 8B 3Misc 1Journal 5Unranked 15

Year	Rank	Type	Title / Venue / Authors
2022	—	`conf`	Convolutional neural network implementations using Vitis AI. CCWC Akihiko Ushiroyama, Minoru Watanabe, Nobuya Watanabe, Akira Nagoya
2018	—	`conf`	Acceleration of Analysis Processing on Decentralized Performance Profiling System Using Virtual Machines. CANDAR Workshops Masao Yamamoto, Kohta Nakashima, Toshihiro Yamauchi, Akira Nagoya, Hideo Taniguchi
2007	J	`jnl`	Network Processor for High-Speed Network and Quick Programming. J. Circuits Syst. Comput. Takahiro Murooka, Akira Nagoya, Toshiaki Miyazaki, Hiroyuki Ochi, Yukihiro Nakamura
2004	J	`jnl`	Dynamically Reconfigurable Logic LSI: PCA-2. IEICE Trans. Inf. Syst. Hideyuki Ito, Ryusuke Konishi, Hiroshi Nakada, Hideyuki Tsuboi, Yuichi Okuyama, Akira Nagoya
2003	—	`conf`	Asynchronous Bit-Serial Datapath for Object-Oriented Reconfigurable Architecture PCA. Asia-Pacific Computer Systems Architecture Conference Kiyoshi Oguri, Yuichiro Shibata, Akira Nagoya
2003	—	`conf`	Concept and implementation of run-time resource management system operating on autonomously reconfigurable architecture. FPT Yoshiki Nakane, Kouichi Nagami, Tsunemichi Shiozawa, Akira Nagoya
2002	J	`jnl`	A Method of Mapping Finite State Machine into PCA Plastic Parts. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Minoru Inamori, Hiroshi Nakada, Ryusuke Konishi, Akira Nagoya, Kiyoshi Oguri
2001	—	`conf`	PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI. ASYNC Ryusuke Konishi, Hideyuki Ito, Hiroshi Nakada, Akira Nagoya, Norbert Imlig, Tsunemichi Shiozawa, Minoru Inamori, Kouichi Nagami, Kiyoshi Oguri
2001	A	`conf`	Scalable space/time-shared stream-processing on the run-time reconfigurable PCA architecture. IPDPS Norbert Imlig, Tsunemichi Shiozawa, Kouichi Nagami, Yoshiki Nakane, Ryusuke Konishi, Hideyuki Ito, Akira Nagoya
2001	—	`conf`	Self-reorganising systems on VLSI circuits. ISCAS (4) Hiroshi Nakada, Hideyuki Ito, Ryusuke Konishi, Akira Nagoya, Kiyoshi Oguri, Tsunemichi Shiozawa, Norbert Imlig
2001	J	`jnl`	Solving satisfiability problems using reconfigurable computing. IEEE Trans. Very Large Scale Integr. Syst. Takayuki Suyama, Makoto Yokoo, Hiroshi Sawada, Akira Nagoya
2000	B	`conf`	A Threshold Logic-Based Reconfigurable Logic Element with a New Programming Technology. FPL Kazuo Aoyama, Hiroshi Sawada, Akira Nagoya, Kazuo Nakajima
2000	B	`conf`	An Implementation of Longest Prefix Matching for IP Router on Plastic Cell Architecture. FPL Tsunemichi Shiozawa, Norbert Imlig, Kouichi Nagami, Kiyoshi Oguri, Akira Nagoya, Hiroshi Nakada
2000	—	`conf`	An efficient framework of using various decomposition methods to synthesize LUT networks and its evaluation. ASP-DAC Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
2000	J	`jnl`	SPFD: A new method to express functional flexibility. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
1999	A	`conf`	A Method for Implementing Fractal Image Compression on Reconfigurable Architecture. FPGA Akihiro Matsuura, Hidehisa Nagano, Akira Nagoya
1999	—	`conf`	Acceleration of Linear Block Code Evaluations Using New Reconfigurable Computing Approach. ASP-DAC Hidehisa Nagano, Takayuki Suyama, Akira Nagoya
1999	—	`conf`	An Efficient Implementation Method of Fractal Image Compression on Dynamically Reconfigurable Architecture. IPPS/SPDP Workshops Hidehisa Nagano, Akihiro Matsuura, Akira Nagoya
1999	—	`conf`	An Integrated Approach for Synthesizing LUT Networks. Great Lakes Symposium on VLSI Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
1999	A	`conf`	Solving Satisfiability Problems on FPGAs Using Experimental Unit Propagation. CP Takayuki Suyama, Makoto Yokoo, Akira Nagoya
1999	—	`conf`	Solving Satisfiability Problems on FPGAs using Experimental Unit Propagation Heuristic. IPPS/SPDP Workshops Takayuki Suyama, Makoto Yokoo, Akira Nagoya
1999	—	`conf`	Summation Algorithms on Constrained Reconfigurable Meshes. ISPAN Akihiro Matsuura, Akira Nagoya
1998	—	`conf`	New Methods to Find Optimal Non-Disjoint Bi-Decompositions. ASP-DAC Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
1998	A	`conf`	Restructuring Logic Representations with Easily Detectable Simple Disjunctive Decompositions. DATE Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya
1998	A	`conf`	Soft Decision Maximum Likelihood Decoders for Binary Linear Block Codes Implemented on FPGAs (Abstract). FPGA Hidehisa Nagano, Takayuki Suyama, Akira Nagoya
1997	—	`conf`	A Hardware/Software Codesign Method for a General Purpose Reconfigurable Co-Processor. CODES Shinji Kimura, Yasufumi Itou, Makoto Hirao, Katsumasa Watanabe, Mitsuteru Yukishita, Akira Nagoya
1997	B	`conf`	Formulation of the Addition-Shift-Sequence Problem and Its Complexity. ISAAC Kaihiro Matsuura, Akira Nagoya
1997	—	`conf`	Restricted Simple Disjunctive Decompositions Based on Grouping Symmetric Variables. Great Lakes Symposium on VLSI Hiroshi Sawada, Shigeru Yamashita, Akira Nagoya
1996	A	`conf`	A new method to express functional permissibilities for LUT based FPGAs and its applications. ICCAD Shigeru Yamashita, Hiroshi Sawada, Akira Nagoya
1996	Misc	`conf`	LUT-based FPGA Technology Mapping using Permissible Functions. VLSI Design Takayuki Suyama, Hiroshi Sawada, Akira Nagoya
1995	A	`conf`	Logic synthesis for look-up table based FPGAs using functional decomposition and support minimization. ICCAD Hiroshi Sawada, Takayuki Suyama, Akira Nagoya
1990	A	`conf`	Multi-Level Optimization for Large Scale ASICS. ICCAD Akira Nagoya, Yukihiro Nakamura, Kiyoshi Oguri, Ryo Nomura