Akira Matsuzawa

204 papers A* 1A 2C 6Journal 106Unranked 89

Year	Rank	Type	Title / Venue / Authors
2023	J	`jnl`	A Brief History of Nyquist Analog-to-Digital Converters. IEICE Trans. Electron. Akira Matsuzawa
2023	J	`jnl`	Sampling circuit issues in A/D converters and challenges for the solution. IEICE Electron. Express Akira Matsuzawa
2023	—	`conf`	Shape the World with Mixed-Signal Integrated Circuits - Past, Present, and Future. ISSCC Akira Matsuzawa
2019	J	`jnl`	A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS. IEEE J. Solid State Circuits Yun Wang, Bangan Liu, Rui Wu, Hanli Liu, Aravind Tharayil Narayanan, Jian Pang, Ning Li, Toru Yoshioka, Yuki Terashima, Haosheng Zhang, Dexian Tang, Makihiko Katsuragi, Daeyoung Lee, Sung Tae Choi, Kenichi Okada, Akira Matsuzawa
2019	—	`conf`	A Universal ADC for Sensor Applications. 3DIC Akira Matsuzawa
2019	J	`jnl`	Type-I Digital Ring-Based PLL Using Loop Delay Compensation and ADC-Based Sampling Phase Detector. IEICE Trans. Electron. Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2018	—	`conf`	A 0.98mW fractional-N ADPLL using 10b isolated constant-slope DTC with FOM of -246dB for IoT applications in 65nm CMOS. ISSCC Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada, Akira Matsuzawa
2018	—	`conf`	A 1.2ps-jitter fully-synthesizable fully-calibrated fractional-N injection-locked PLL using true arbitrary nonlinearity calibration technique. CICC Bangan Liu, Huy Cu Ngo, Kengo Nakata, Wei Deng, Yuncheng Zhang, Junjun Qiu, Toru Yoshioka, Jun Emmei, Haosheng Zhang, Jian Pang, Aravind Tharayil Narayanan, Dongsheng Yang, Hanli Liu, Kenichi Okada, Akira Matsuzawa
2018	J	`jnl`	A 12.8-ns-Latency DDFS MMIC With Frequency, Phase, and Amplitude Modulations in 65-nm CMOS. IEEE J. Solid State Circuits Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa
2018	—	`conf`	A 120Gb/s 16QAM CMOS millimeter-wave wireless transceiver. ISSCC Korkut Kaan Tokgoz, Shotaro Maki, Jian Pang, Noriaki Nagashima, Ibrahim Abdo, Seitaro Kawai, Takuya Fujimura, Yoichi Kawano, Toshihide Suzuki, Taisuke Iwai, Kenichi Okada, Akira Matsuzawa
2018	C	`conf`	A 14-b, 850fs Fully Synthesizable Stochastic-Based Branching Time-to-Digital Converter in 65nm CMOS. ISCAS Jian Sen Teh, Liter Siek, Abdel Martinez Alonso, Anugerah Firdauzi, Akira Matsuzawa
2018	J	`jnl`	A 28-GHz Fractional-N Frequency Synthesizer with Reference and Frequency Doublers for 5G Mobile Communications in 65nm CMOS. IEICE Trans. Electron. Hanli Liu, Teerachot Siriburanon, Kengo Nakata, Wei Deng, Ju Ho Son, Dae Young Lee, Kenichi Okada, Akira Matsuzawa
2018	—	`conf`	A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier. VLSI Circuits Masaya Miyahara, Yukiya Endo, Kenichi Okada, Akira Matsuzawa
2018	J	`jnl`	A 72.4dB-SNDR 20MHz-Bandwidth Continuous-Time ΔΣ ADC with High-Linearity Gm-Cells. IEICE Trans. Electron. Tohru Kaneko, Yuya Kimura, Masaya Miyahara, Akira Matsuzawa
2018	J	`jnl`	A 7GS/s Complete-DDFS-Solution in 65nm CMOS. IEICE Trans. Electron. Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa
2018	J	`jnl`	A Consideration of Threshold Voltage Mismatch Effects and a Calibration Technique for Current Mirror Circuits. IEICE Trans. Electron. Tohru Kaneko, Koji Hirose, Akira Matsuzawa
2018	J	`jnl`	A Low-Power Pulse-Shaped Duobinary ASK Modulator for IEEE 802.11ad Compliant 60GHz Transmitter in 65nm CMOS. IEICE Trans. Electron. Bangan Liu, Yun Wang, Jian Pang, Haosheng Zhang, Dongsheng Yang, Aravind Tharayil Narayanan, Dae Young Lee, Sung Tae Choi, Rui Wu, Kenichi Okada, Akira Matsuzawa
2018	—	`conf`	An ADPLL-centric bluetooth low-energy transceiver with 2.3mW interference-tolerant hybrid-loop receiver and 2.9mW single-point polar transmitter in 65nm CMOS. ISSCC Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Wei Deng, Rui Wu, Kenichi Okada, Akira Matsuzawa
2018	J	`jnl`	Design of low-loss 60 GHz integrated antenna switch in 65 nm CMOS. IEICE Electron. Express Korkut Kaan Tokgoz, Seitaro Kawai, Kenichi Okada, Akira Matsuzawa
2018	J	`jnl`	SAR+ΔΣ ADCs with open-loop integrator using dynamic amplifier. IEICE Electron. Express Akira Matsuzawa, Masaya Miyahara
2017	—	`conf`	24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalance. ISSCC Jian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon, Aravind Tharayil Narayanan, Nurul Fajri, Tohru Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang, Rui Wu, Ning Li, Korkut Kaan Tokgoz, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2017	J	`jnl`	64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay. IEEE J. Solid State Circuits Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang, Jian Pang, Ning Li, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2017	—	`conf`	8.5 A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDO. ISSCC Huy Cu Ngo, Kengo Nakata, Toru Yoshioka, Yuki Terashima, Kenichi Okada, Akira Matsuzawa
2017	J	`jnl`	A 20-GHz Differential Push-Push VCO for 60-GHz Frequency Synthesizer toward 256 QAM Wireless Transmission in 65-nm CMOS. IEICE Trans. Electron. Yun Wang, Makihiko Katsuragi, Kenichi Okada, Akira Matsuzawa
2017	—	`conf`	A 7GS/s direct digital frequency synthesizer with a two-times interleaved RDAC in 65nm CMOS. ESSCIRC Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa
2017	J	`jnl`	A Fully-Synthesizable 10.06Gbps 16.1mW Injection-Locked CDR in 28nm FDSOI. IEICE Trans. Electron. Aravind Tharayil Narayanan, Wei Deng, Dongsheng Yang, Rui Wu, Kenichi Okada, Akira Matsuzawa
2017	J	`jnl`	A Wide Bandwidth Current Mode Filter Technique Using High Power Efficiency Current Amplifiers with Complementary Input. IEICE Trans. Electron. Tohru Kaneko, Yuya Kimura, Masaya Miyahara, Akira Matsuzawa
2017	—	`conf`	A high-speed DDFS MMIC with frequency, phase and amplitude modulations in 65nm CMOS. A-SSCC Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa
2017	—	`conf`	An 84 dB dynamic range 62.5-625 kHz bandwidth clock-scalable noise-shaping SAR ADC with open-loop integrator using dynamic amplifier. CICC Masaya Miyahara, Akira Matsuzawa
2017	—	`conf`	An HDL-synthesized injection-locked PLL using LC-based DCO for on-chip clock generation. ASP-DAC Dongsheng Yang, Wei Deng, Bangan Liu, Aravind Tharayil Narayanan, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa
2017	—	`conf`	An automatic dynamic range adaptation algorithm for capacitive sensor interface circuits. ECCTD Tuan Minh Vo, Akira Matsuzawa
2017	J	`jnl`	High Resolution Mixed-Domain Delta-Sigma Time-to-Digital Converter Using Compensated Charge-Pump Integrator. IEICE Trans. Electron. Anugerah Firdauzi, Zule Xu, Masaya Miyahara, Akira Matsuzawa
2017	J	`jnl`	Physical-Weight-Based Measurement Methodology Suppressing Noise or Reducing Test Time for High-Resolution Low-Speed ADCs. IEICE Trans. Electron. Mitsutoshi Sugawara, Zule Xu, Akira Matsuzawa
2017	—	`conf`	SAR+ΔΣ ADC with open-loop integrator using dynamic amplifier. ASICON Akira Matsuzawa, Masaya Miyahara
2017	—	`conf`	Ultra-high-data-rate 60-GHz CMOS transceiver for future radio access network. ASICON Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang, Jian Pang, Ning Li, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2017	—	`conf`	W-band ultra-high data-rate 65nm CMOS wireless transceiver. ASP-DAC Korkut Kaan Tokgoz, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yoichi Kawano, Toshihide Suzuki, Taisuke Iwai, Kenichi Okada, Akira Matsuzawa
2016	—	`conf`	13.3 A 56Gb/s W-band CMOS wireless transceiver. ISSCC Korkut Kaan Tokgoz, Shotaro Maki, Seitaro Kawai, Noriaki Nagashima, Jun Emmei, Masato Dome, Hisashi Kato, Jian Pang, Yoichi Kawano, Toshihide Suzuki, Taisuke Iwai, Yuuki Seo, Kimsrun Lim, Shinji Sato, Ning Li, Kengo Nakata, Kenichi Okada, Akira Matsuzawa
2016	—	`conf`	13.6 A 42Gb/s 60GHz CMOS transceiver for IEEE 802.11ay. ISSCC Rui Wu, Seitaro Kawai, Yuuki Seo, Nurul Fajri, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Teerachot Siriburanon, Shoutarou Maki, Bangan Liu, Yun Wang, Noriaki Nagashima, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016	J	`jnl`	A 0.0055mm IEICE Trans. Electron. Dongsheng Yang, Tomohiro Ueno, Wei Deng, Yuki Terashima, Kengo Nakata, Aravind Tharayil Narayanan, Rui Wu, Kenichi Okada, Akira Matsuzawa
2016	J	`jnl`	A 10-bit 6.8-GS/s Direct Digital Frequency Synthesizer Employing Complementary Dual-Phase Latch-Based Architecture. IEICE Trans. Electron. Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa
2016	—	`conf`	A 2 A-SSCC Zhijie Chen, Masaya Miyahara, Akira Matsuzawa
2016	—	`conf`	A 2 GHz 3.1 mW type-I digital ring-based PLL. ESSCIRC Zule Xu, Anugerah Firdauzi, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016	J	`jnl`	A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture. IEEE J. Solid State Circuits Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016	J	`jnl`	A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC. IEEE J. Solid State Circuits Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016	C	`conf`	A 74.9 dB SNDR 1 MHz bandwidth 0.9 mW delta-sigma time-to-digital converter using charge pump and SAR ADC. ISCAS Anugerah Firdauzi, Zule Xu, Masaya Miyahara, Akira Matsuzawa
2016	—	`conf`	A 76-dB-DR 6.8-mW 20-MHz bandwidth CT ΔΣ ADC with a high-linearity Gm-C filter. ESSCIRC Tohru Kaneko, Yuya Kimura, Koji Hirose, Masaya Miyahara, Akira Matsuzawa
2016	J	`jnl`	A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers. IEEE J. Solid State Circuits Lilan Yu, Masaya Miyahara, Akira Matsuzawa
2016	—	`conf`	A 9-bit 500-MS/s 6.0-mW dynamic pipelined ADC using time-domain linearized dynamic amplifiers. A-SSCC Lilan Yu, Masaya Miyahara, Akira Matsuzawa
2016	J	`jnl`	A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC. IEICE Trans. Electron. Zhijie Chen, Masaya Miyahara, Akira Matsuzawa
2016	J	`jnl`	A Design of Op-Amp Free SAR-VCO Hybrid ADC with 2 IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yu Hou, Zhijie Chen, Masaya Miyahara, Akira Matsuzawa
2016	J	`jnl`	A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB. IEEE J. Solid State Circuits Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Kengo Nakata, Wei Deng, Kenichi Okada, Akira Matsuzawa
2016	J	`jnl`	A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad. IEEE J. Solid State Circuits Teerachot Siriburanon, Satoshi Kondo, Makihiko Katsuragi, Hanli Liu, Kento Kimura, Wei Deng, Kenichi Okada, Akira Matsuzawa
2016	—	`conf`	A noise reduction technique for divider-less fractional-N frequency synthesizer using phase-interpolation technique. ASP-DAC Aravind Tharayil Narayanan, Makihiko Katsuragi, Kengo Nakata, Yuki Terashima, Kenichi Okada, Akira Matsuzawa
2016	—	`conf`	A stability-improved single-opamp third-order ΣΔ modulator by using a fully-passive noise-shaping SAR ADC and passive adder. ESSCIRC Zhijie Chen, Masaya Miyahara, Akira Matsuzawa
2016	—	`conf`	An LC-DCO based synthesizable injection-locked PLL with an FoM of -250.3dB. ESSCIRC Dongsheng Yang, Wei Deng, Bangan Liu, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa
2016	—	`conf`	An LO-buffer-less 60-GHz CMOS transmitter with oscillator pulling mitigation. A-SSCC Rui Wu, Jian Pang, Yuuki Seo, Kento Kimura, Seitaro Kawai, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2016	—	`conf`	An automatic place-and-routed two-stage fractional-N injection-locked PLL using soft injection. ASP-DAC Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa
2016	J	`jnl`	Fully Passive Noise Shaping Techniques in a Charge-Redistribution SAR ADC. IEICE Trans. Electron. Zhijie Chen, Masaya Miyahara, Akira Matsuzawa
2016	J	`jnl`	Highly Linear Open-Loop Amplifiers Using Nonlinearity Cancellation and Gain Adapting Techniques. IEICE Trans. Electron. Lilan Yu, Masaya Miyahara, Akira Matsuzawa
2016	J	`jnl`	Synthesis and Automatic Layout of Resistive Digital-to-Analog Converter Based on Mixed-Signal Slice Cell. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Mitsutoshi Sugawara, Kenji Mori, Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	14.1 A 0.048mm ISSCC Wei Deng, Dongsheng Yang, Aravind Tharayil Narayanan, Kengo Nakata, Teerachot Siriburanon, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	19.5 An HCI-healing 60GHz CMOS transceiver. ISSCC Rui Wu, Seitaro Kawai, Yuuki Seo, Kento Kimura, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	25.2 A 2.2GHz -242dB-FOM 4.2mW ADC-PLL using digital sub-sampling architecture. ISSCC Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	A 28-GHz fractional-N frequency synthesizer with reference and frequency doublers for 5G cellular. ESSCIRC Teerachot Siriburanon, Hanli Liu, Kengo Nakata, Wei Deng, Ju Ho Son, Dae Young Lee, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	A 3.6 GHz fractional-N digital PLL using SAR-ADC-based TDC with-110 dBc/Hz in-band phase noise. A-SSCC Zule Xu, Masaya Miyahara, Akira Matsuzawa
2015	—	`conf`	A 58.3-to-65.4 GHz 34.2 mW sub-harmonically injection-locked PLL with a sub-sampling phase detection. ASP-DAC Teerachot Siriburanon, Tomohiro Ueno, Kento Kimura, Satoshi Kondo, Wei Deng, Kenichi Okada, Akira Matsuzawa
2015	J	`jnl`	A 60-GHz CMOS Transmitter with Gain-Enhanced On-Chip Antenna for Short-Range Wireless Interconnections. IEICE Trans. Electron. Rui Wu, Wei Deng, Shinji Sato, Takuichi Hirano, Ning Li, Takeshi Inoue, Hitoshi Sakane, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	A 9-bit 1.8-GS/s pipelined ADC using linearized open-loop amplifiers. A-SSCC Lilan Yu, Masaya Miyahara, Akira Matsuzawa
2015	—	`conf`	A 9.35-ENOB, 14.8 fJ/conv.-step fully-passive noise-shaping SAR ADC. VLSIC Zhijie Chen, Masaya Miyahara, Akira Matsuzawa
2015	J	`jnl`	A Circuit Technique for Enhancing Gain of Complementary Input Operational Amplifier with High Power Efficiency. IEICE Trans. Electron. Tohru Kaneko, Masaya Miyahara, Akira Matsuzawa
2015	J	`jnl`	A Constant-Current-Controlled Class-C Voltage-Controlled Oscillator using Self-Adjusting Replica Bias Circuit. IEICE Trans. Electron. Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa
2015	J	`jnl`	A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique. IEEE J. Solid State Circuits Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of -246dB. ESSCIRC Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Kengo Nakata, Wei Deng, Kenichi Okada, Akira Matsuzawa
2015	J	`jnl`	A fully synthesizable injection-locked PLL with feedback current output DAC in 28 nm FDSOI. IEICE Electron. Express Dongsheng Yang, Wei Deng, Aravind Tharayil Narayanan, Rui Wu, Bangan Liu, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	A novel direct digital frequency synthesizer employing complementary dual-phase latch-based architecture. ASICON Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa
2015	—	`conf`	A tail-current modulated VCO with adaptive-bias scheme. ASP-DAC Aravind Tharayil Narayanan, Wei Deng, Kenichi Okada, Akira Matsuzawa
2015	J	`jnl`	An AM-PM Noise Mitigation Technique in Class-C VCO. IEICE Trans. Electron. Kento Kimura, Aravind Tharayil Narayanan, Kenichi Okada, Akira Matsuzawa
2015	J	`jnl`	An All-Digital Reconfigurable Time-Domain ADC for Low-Voltage Sensor Interface in 65nm CMOS Technology. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yu Hou, Takamoto Watanabe, Masaya Miyahara, Akira Matsuzawa
2015	—	`conf`	An HDL-synthesized gated-edge-injection PLL with a current output DAC. ASP-DAC Dongsheng Yang, Wei Deng, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa
2015	J	`jnl`	An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers. IEEE J. Solid State Circuits James Lin, Daehwa Paik, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa
2015	—	`conf`	Automated design strategy for high performance mixed signal circuits. ASICON Akira Matsuzawa
2015	J	`jnl`	Characterization of Crossing Transmission Line Using Two-Port Measurements for Millimeter-Wave CMOS Circuit Design. IEICE Trans. Electron. Korkut Kaan Tokgoz, Kimsrun Lim, Seitarou Kawai, Nurul Fajri, Kenichi Okada, Akira Matsuzawa
2015	—	`conf`	High data rate 60 GHz CMOS transceiver design. ISPACS Akira Matsuzawa
2015	J	`jnl`	Sub-Picosecond Resolution and High-Precision TDC for ADPLLs Using Charge Pump and SAR-ADC. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Zule Xu, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa
2015	—	`conf`	Substrate noise isolation improvement by helium-3 ion irradiation technique in a triple-well CMOS process. ESSDERC Ning Li, Takeshi Inoue, Takuichi Hirano, Jian Pang, Rui Wu, Kenichi Okada, Hitoshi Sakane, Akira Matsuzawa
2015	J	`jnl`	Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product. IEEE Trans. Very Large Scale Integr. Syst. James Lin, Ibuki Mano, Masaya Miyahara, Akira Matsuzawa
2014	—	`conf`	15.1 A 0.0066mm ISSCC Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	20.3 A 64-QAM 60GHz CMOS transceiver with 4-channel bonding. ISSCC Kenichi Okada, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Satoshi Kondo, Tomohiro Ueno, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Rui Wu, Masaya Miyahara, Akira Matsuzawa
2014	—	`conf`	22.6 A 2.2GS/s 7b 27.4mW time-based folding-flash ADC with resistively averaged voltage-to-time amplifiers. ISSCC Masaya Miyahara, Ibuki Mano, Masaaki Nakayama, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	A 0.011 mm A-SSCC Aravind Tharayil Narayanan, Wei Deng, Dongsheng Yang, Rui Wu, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	A 0.015-mm A-SSCC Rui Wu, Qinghong Bu, Wei Deng, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	A 0.5-to-1 V 9-bit 15-to-90 MS/s digitally interpolated pipelined-SAR ADC using dynamic amplifier. A-SSCC James Lin, Zule Xu, Masaya Miyahara, Akira Matsuzawa
2014	J	`jnl`	A 7-bit 1-GS/s Flash ADC with Background Calibration. IEICE Trans. Electron. Sanroku Tsukamoto, Masaya Miyahara, Akira Matsuzawa
2014	J	`jnl`	A Compact and Low-Power Fractionally Injection-Locked Quadrature Frequency Synthesizer Using a Self-Synchronized Gating Injection Technique for Software-Defined Radios. IEEE J. Solid State Circuits Wei Deng, Shoichi Hara, Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2014	J	`jnl`	A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration. IEEE J. Solid State Circuits Ahmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2014	J	`jnl`	A Variable-Supply-Voltage 60-GHz PA with Consideration of HCI Issues for TDD Operation. IEICE Trans. Electron. Rui Wu, Yuuki Tsukui, Ryo Minami, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generation. ASP-DAC Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	A pulse-driven LC-VCO with a figure-of-merit of -192dBc/Hz. ESSCIRC Aravind Tharayil Narayanan, Kento Kimura, Wei Deng, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	A swing-enhanced current-reuse class-C VCO with dynamic bias control circuits. ASP-DAC Teerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa
2014	—	`conf`	All-digital 0.016mm ICECS Takamoto Watanabe, Yu Hou, Masaya Miyahara, Akira Matsuzawa
2014	J	`jnl`	An Ultra-Low-Voltage, Wide Signal Swing, and Clock-Scalable Dynamic Amplifier Using a Common-Mode Detection Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. James Lin, Masaya Miyahara, Akira Matsuzawa
2014	J	`jnl`	Injection Locked Charge-Pump PLL with a Replica of the Ring Oscillator. IEICE Trans. Electron. Jeonghoon Han, Masaya Miyahara, Akira Matsuzawa
2014	—	`conf`	Radio receiver front-end using time-based all-digital ADC (TAD). ICECS Tomohito Terasawa, Yuji Kamiya, Hiroyuki Kawashima, Kenichiro Imai, Masanobu Suzuki, Takamoto Watanabe, Nobuyuki Taguchi, Manabu Sawada, Yu Hou, Yoshiyuki Hirooka, Hong Phuc Ninh, Masaya Miyahara, Akira Matsuzawa
2013	—	`conf`	A 0.022mm ISSCC Wei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa
2013	—	`conf`	A 0.55 V 7-bit 160 MS/s interpolated pipeline ADC using dynamic amplifiers. CICC James Lin, Daehwa Paik, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa
2013	—	`conf`	A 0.84ps-LSB 2.47mW time-to-digital converter using charge pump and SAR-ADC. CICC Zule Xu, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa
2013	—	`conf`	A 1 ps-resolution integrator-based time-to-digital converter using a SAR-ADC in 90nm CMOS. NEWCAS Zule Xu, Masaya Miyahara, Akira Matsuzawa
2013	J	`jnl`	A 12-bit Interpolated Pipeline ADC Using Body Voltage Controlled Amplifier. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hyunui Lee, Masaya Miyahara, Akira Matsuzawa
2013	—	`conf`	A 12-bit interpolated pipeline ADC using body voltage controlled amplifier. NEWCAS Hyunui Lee, Masaya Miyahara, Akira Matsuzawa
2013	—	`conf`	A 13.2% locking-range divide-by-6, 3.1mW, ILFD using even-harmonic-enhanced direct injection technique for millimeter-wave PLLs. ESSCIRC Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2013	J	`jnl`	A 20 GHz Push-Push Voltage-Controlled Oscillator Using Second-Harmonic Peaking Technique for a 60 GHz Frequency Synthesizer. IEICE Trans. Electron. Teerachot Siriburanon, Takahiro Sato, Ahmed Musa, Wei Deng, Kenichi Okada, Akira Matsuzawa
2013	J	`jnl`	A 6 bit, 7 mW, 700 MS/s Subranging ADC Using CDAC and Gate-Weighted Interpolation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Hyunui Lee, Yusuke Asada, Masaya Miyahara, Akira Matsuzawa
2013	—	`conf`	A 60 GHz up-conversion mixer using asymmetric layout with -41.1 dBc LO leakage. LASCAS Yuki Tsukui, Kenichi Okada, Akira Matsuzawa
2013	J	`jnl`	A Low-Noise High-Dynamic Range Charge Sensitive Amplifier for Gas Particle Detector Pixel Readout LSIs. IEICE Trans. Electron. Fei Li, Masaya Miyahara, Akira Matsuzawa
2013	J	`jnl`	A Study of Stability and Phase Noise of Tail Capacitive-Feedback VCOs. IEICE Trans. Electron. Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2013	J	`jnl`	A Sub-Harmonic Injection-Locked Quadrature Frequency Synthesizer With Frequency Calibration Scheme for Millimeter-Wave TDD Transceivers. IEEE J. Solid State Circuits Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2013	J	`jnl`	A Time-Domain Architecture and Design Method of High Speed A-to-D Converters with Standard Cells. IEICE Trans. Electron. Masao Takayama, Shiro Dosho, Noriaki Takeda, Masaya Miyahara, Akira Matsuzawa
2013	—	`conf`	A fractional-N harmonic injection-locked frequency synthesizer with 10MHz-6.6GHz quadrature outputs for software-defined radios. ASP-DAC Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2013	—	`conf`	A full 4-channel 60 GHz direct-conversion transceiver. ASP-DAC Seitaro Kawai, Ryo Minami, Ahmed Musa, Takahiro Sato, Ning Li, Tatsuya Yamaguchi, Yasuaki Takeuchi, Yuki Tsukui, Kenichi Okada, Akira Matsuzawa
2013	—	`conf`	A sub-harmonic injection-locked frequency synthesizer with frequency calibration scheme for use in 60GHz TDD transceivers. ASP-DAC Teerachot Siriburanon, Wei Deng, Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2013	J	`jnl`	Class-C VCO With Amplitude Feedback Loop for Robust Start-Up and Enhanced Oscillation Swing. IEEE J. Solid State Circuits Wei Deng, Kenichi Okada, Akira Matsuzawa
2013	J	`jnl`	Design of CMOS Low-Noise Analog Circuits for Particle Detector Pixel Readout LSIs. IEICE Trans. Electron. Fei Li, Masaya Miyahara, Akira Matsuzawa
2013	J	`jnl`	Design of Interpolated Pipeline ADC Using Low-Gain Open-Loop Amplifiers. IEICE Trans. Electron. Hyunui Lee, Masaya Miyahara, Akira Matsuzawa
2013	J	`jnl`	Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry. IEEE J. Solid State Circuits Kenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, Akira Matsuzawa
2012	J	`jnl`	A 0.5-V, 0.05-to-3.2 GHz LC-Based Clock Generator for Substituting Ring Oscillators under Low-Voltage Condition. IEICE Trans. Electron. Wei Deng, Kenichi Okada, Akira Matsuzawa
2012	J	`jnl`	A 24 dB Gain 51-68 GHz Common Source Low Noise Amplifier Using Asymmetric-Layout Transistors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ning Li, Keigo Bunsen, Naoki Takayama, Qinghong Bu, Toshihide Suzuki, Masaru Sato, Yoichi Kawano, Tatsuya Hirose, Kenichi Okada, Akira Matsuzawa
2012	—	`conf`	A 58.1-to-65.0GHz frequency synthesizer with background calibration for millimeter-wave TDD transceivers. ESSCIRC Wei Deng, Teerachot Siriburanon, Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2012	—	`conf`	A 60-GHz 16QAM 11Gbps direct-conversion transceiver in 65nm CMOS. ASP-DAC Ryo Minami, Hiroki Asada, Ahmed Musa, Takahiro Sato, Ning Li, Tatsuya Yamaguchi, Yasuaki Takeuchi, Win Chaivipas, Kenichi Okada, Akira Matsuzawa
2012	J	`jnl`	A 83-dB SFDR 10-MHz Bandwidth Continuous-Time Delta-Sigma Modulator Employing a One-Element-Shifting Dynamic Element Matching. IEICE Trans. Electron. Hong Phuc Ninh, Masaya Miyahara, Akira Matsuzawa
2012	J	`jnl`	A Dual-Conduction Class-C VCO for a Low Supply Voltage. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Kenichi Okada, You Nomiyama, Rui Murakami, Akira Matsuzawa
2012	—	`conf`	A PVT-robust feedback class-C VCO using an oscillation swing enhancement technique. ASP-DAC Wei Deng, Kenichi Okada, Akira Matsuzawa
2012	—	`conf`	A Progressive Mixing 20GHz ILFD with wide locking range for higher division ratios. ASP-DAC Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2012	J	`jnl`	A Specific Distortion Pattern of Flash ADCs Identified by Discriminating Time-Domain Analysis. IEEE Trans. Instrum. Meas. Yuji Gendai, Akira Matsuzawa
2012	J	`jnl`	A Wideband Common-Gate Low-Noise Amplifier Using Capacitive Feedback. IEICE Trans. Electron. Toshihiko Ito, Kenichi Okada, Akira Matsuzawa
2012	—	`conf`	A full 4-channel 6.3Gb/s 60GHz direct-conversion transceiver with low-power analog and digital baseband circuitry. ISSCC Kenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, Akira Matsuzawa
2012	J	`jnl`	An Analysis on a Dynamic Amplifier and Calibration Methods for a Pseudo-Differential Dynamic Comparator. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Daehwa Paik, Masaya Miyahara, Akira Matsuzawa
2012	J	`jnl`	Evaluation of L-2L De-Embedding Method Considering Misalignment of Contact Position for Millimeter-Wave CMOS Circuit Design. IEICE Trans. Electron. Qinghong Bu, Ning Li, Kenichi Okada, Akira Matsuzawa
2012	J	`jnl`	Inter-Stage Tunable Notch Filter for a Multi-Band WCDMA Receiver. IEICE Trans. Electron. Toshihiko Ito, Masaki Kanemaru, Satoshi Furuya, Dong Ta Ngoc Huy, Kenichi Okada, Akira Matsuzawa
2012	J	`jnl`	Two-Stage Band-Selectable CMOS Power Amplifiers Using Inter-Stage Frequency Tuning. IEICE Trans. Electron. Jee Young Hong, Daisuke Imanishi, Kenichi Okada, Akira Matsuzawa
2011	J	`jnl`	A 14.3% PAE parallel class-A and AB 60GHz CMOS PA. IEICE Electron. Express Ning Li, Kota Matsushita, Kenichi Okada, Akira Matsuzawa
2011	C	`conf`	A 15.5 dB, wide signal swing, dynamic amplifier using a common-mode voltage detection technique. ISCAS James Lin, Masaya Miyahara, Akira Matsuzawa
2011	—	`conf`	A 20GHz ILFD with locking range of 31% for divide-by-4 and 15% for divide-by-8 using progressive mixing. A-SSCC Ahmed Musa, Kenichi Okada, Akira Matsuzawa
2011	—	`conf`	A 58-63.6GHz quadrature PLL frequency synthesizer using dual-injection technique. ASP-DAC Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, Akira Matsuzawa
2011	J	`jnl`	A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c. IEEE J. Solid State Circuits Kenichi Okada, Ning Li, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada, Naoki Takayama, Shogo Ito, Win Chaivipas, Ryo Minami, Tatsuya Yamaguchi, Yasuaki Takeuchi, Hiroyuki Yamagishi, Makoto Noda, Akira Matsuzawa
2011	—	`conf`	A 60GHz 16Gb/s 16QAM low-power direct-conversion transceiver using capacitive cross-coupling neutralization in 65 nm CMOS. A-SSCC Hiroki Asada, Keigo Bunsen, Kota Matsushita, Rui Murakami, Qinghong Bu, Ahmed Musa, Takahiro Sato, Tatsuya Yamaguchi, Ryo Minami, Toshihiko Ito, Kenichi Okada, Akira Matsuzawa
2011	—	`conf`	A 60GHz 16QAM/8PSK/QPSK/BPSK direct-conversion transceiver for IEEE 802.15.3c. ISSCC Kenichi Okada, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada, Naoki Takayama, Ning Li, Shogo Ito, Win Chaivipas, Ryo Minami, Akira Matsuzawa
2011	J	`jnl`	A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications. IEEE J. Solid State Circuits Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, Akira Matsuzawa
2011	—	`conf`	A feedback class-C VCO with robust startup condition over PVT variations and enhanced oscillation swing. ESSCIRC Wei Deng, Kenichi Okada, Akira Matsuzawa
2011	—	`conf`	A new figure of Merit of LC oscilators considering frequency tuning range. ASICON Takahiro Sato, Kenichi Okada, Akira Matsuzawa
2011	—	`conf`	A time-domain architecture and design method of high speed A-to-D converters with standard cells. A-SSCC Masao Takayama, Shiro Dosho, Noriaki Takeda, Masaya Miyahara, Akira Matsuzawa
2011	—	`conf`	An analysis on a pseudo-differential dynamic comparator with load capacitance calibration. ASICON Daehwa Paik, Masaya Miyahara, Akira Matsuzawa
2011	J	`jnl`	An ultra-compact LC-VCO using a stacked-spiral inductor. IEICE Electron. Express Rui Murakami, Toshihiko Ito, Kenichi Okada, Akira Matsuzawa
2011	—	`conf`	An ultra-low-voltage LC-VCO with a frequency extension circuit for future 0.5-V clock generation. ASP-DAC Wei Deng, Kenichi Okada, Akira Matsuzawa
2011	—	`conf`	Energy efficient ADC design with low voltage operation. ASICON Akira Matsuzawa
2011	J	`jnl`	Measurement of Integrated PA-to-LNA Isolation on Si CMOS Chip. IEICE Trans. Electron. Ryo Minami, Jee Young Hong, Kenichi Okada, Akira Matsuzawa
2011	J	`jnl`	Topology and Design Considerations of 60 GHz CMOS LNAs for Noise Performance Improving. IEICE Trans. Electron. Ning Li, Qinghong Bu, Kota Matsushita, Naoki Takayama, Shogo Ito, Kenichi Okada, Akira Matsuzawa
2011	J	`jnl`	Tunable CMOS Power Amplifiers for Reconfigurable Transceivers. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Jee Young Hong, Daisuke Imanishi, Kenichi Okada, Akira Matsuzawa
2010	—	`conf`	A 2-6 GHz fully integrated tunable CMOS power amplifier for multi-standard transmitters. ASP-DAC Daisuke Imanishi, Jee Young Hong, Kenichi Okada, Akira Matsuzawa
2010	—	`conf`	A 24 dB gain 51-68 GHz CMOS low noise amplifier using asymmetric-layout transistors. ESSCIRC Ning Li, Keigo Bunsen, Naoki Takayama, Qinghong Bu, Toshihide Suzuki, Masaru Sato, Tatsuya Hirose, Kenichi Okada, Akira Matsuzawa
2010	—	`conf`	A 60GHz direct-conversion transmitter in 65nm CMOS technology. ASP-DAC Naoki Takayama, Kota Matsushita, Shogo Ito, Ning Li, Kenichi Okada, Akira Matsuzawa
2010	J	`jnl`	A De-Embedding Method Using Different-Length Transmission Lines for mm-Wave CMOS Device Modeling. IEICE Trans. Electron. Naoki Takayama, Kota Matsushita, Shogo Ito, Ning Li, Keigo Bunsen, Kenichi Okada, Akira Matsuzawa
2010	J	`jnl`	A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator. IEEE J. Solid State Circuits Kazuo Matsukawa, Yosuke Mitani, Masao Takayama, Koji Obata, Shiro Dosho, Akira Matsuzawa
2010	J	`jnl`	A Self-Calibration Technique for Capacitor Mismatch Errors of an Interleaved SAR ADC. IEICE Trans. Electron. Yasuhide Kuramochi, Masayuki Kawabata, Koichiro Uekusa, Akira Matsuzawa
2010	J	`jnl`	A Wide-Tunable LC-Based Voltage-Controlled Oscillator Using a Divide-by-N Injection-Locked Frequency Divider. IEICE Trans. Electron. Shoichi Hara, Kenichi Okada, Akira Matsuzawa
2010	J	`jnl`	An 8-Bit 600-MSps Flash ADC Using Interpolating and Background Self-Calibrating Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Daehwa Paik, Yusuke Asada, Masaya Miyahara, Akira Matsuzawa
2010	J	`jnl`	Analysis of Phase Noise Degradation Considering Switch Transistor Capacitances for CMOS Voltage Controlled Oscillators. IEICE Trans. Electron. Rui Murakami, Shoichi Hara, Kenichi Okada, Akira Matsuzawa
2010	J	`jnl`	Evaluation of a Multi-Line De-Embedding Technique up to 110 GHz for Millimeter-Wave CMOS Circuit Design. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Ning Li, Kota Matsushita, Naoki Takayama, Shogo Ito, Kenichi Okada, Akira Matsuzawa
2010	J	`jnl`	The Optimum Design Methodology of Low-Phase-Noise LC-VCO Using Multiple-Divide Technique. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Shoichi Hara, Rui Murakami, Kenichi Okada, Akira Matsuzawa
2009	J	`jnl`	A 0.027-mm IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Yasuhide Kuramochi, Akira Matsuzawa, Masayuki Kawabata
2009	—	`conf`	An experimental 0.6-V 57.5-fJ/conversion-step 250-kS/s 8-bit rail-to-rail successive approximation ADC in 0.18µm CMOS. ICECS Christian Jesús B. Fayomi, Gilson I. Wirth, David M. Binkley, Akira Matsuzawa
2009	—	`conf`	Development of baseband processing SoC with ultrahigh-speed QAM modem and broadband radio system for demonstration experiment thereof. ICECS Kaziiya Kojima, Yasuhiro Toriyama, Toru Taniguchi, Masaya Miyahara, Akira Matsuzawa
2008	C	`conf`	"The flipped voltage follower"-based low voltage fully differential CMOS sample-and-hold circuit. ISCAS Christian Jesús B. Fayomi, Gilson I. Wirth, Jaime Ramírez-Angulo, Akira Matsuzawa
2008	—	`conf`	A CMOS direct sampling mixer using Switched Capacitor Filter technique for software-defined radio. ASP-DAC Hong Phuc Ninh, Takashi Moue, Takashi Kurashina, Kenichi Okada, Akira Matsuzawa
2008	J	`jnl`	A Performance Model for the Design of Pipelined ADCs with Consideration of Overdrive Voltage and Slewing. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Masaya Miyahara, Akira Matsuzawa
2008	J	`jnl`	Analysis of CMOS Transconductance Amplifiers for Sampling Mixers. IEICE Trans. Electron. Ning Li, Win Chaivipas, Kenichi Okada, Akira Matsuzawa
2008	C	`conf`	Design space exploration of low-phase-noise LC-VCO using multiple-divide technique. ISCAS Shoichi Hara, Takeshi Ito, Kenichi Okada, Akira Matsuzawa
2008	J	`jnl`	Digital-Centric RF CMOS Technologies. IEICE Trans. Electron. Akira Matsuzawa
2008	J	`jnl`	RF Variable-Gain Amplifiers and AGC Loops for Digital TV Receivers. IEICE Trans. Electron. Kunihiko Iizuka, Masato Koutani, Takeshi Mitsunaka, Hiroshi Kawamura, Shinji Toyoyama, Masayuki Miyamoto, Akira Matsuzawa
2008	J	`jnl`	Spatial Sensitivity of Capacitors in Distributed Resonators and Its Application to Fine and Wide Frequency Tuning Digital Controlled Oscillators. IEICE Trans. Electron. Win Chaivipas, Kenichi Okada, Akira Matsuzawa
2007	J	`jnl`	A Study on Fully Digital Clock Data Recovery Utilizing Time to Digital Converter. IEICE Trans. Electron. Philipus Chandra Oh, Akira Matsuzawa, Win Chaivipas
2007	J	`jnl`	Analysis and Design of Direct Reference Feed-Forward Compensation for Fast-Settling All-Digital Phase-Locked Loop. IEICE Trans. Electron. Win Chaivipas, Akira Matsuzawa
2007	J	`jnl`	Design Challenges of Analog-to-Digital Converters in Nanoscale CMOS. IEICE Trans. Electron. Akira Matsuzawa
2007	J	`jnl`	Digital Calibration Method for Binary-Weighted Current-Steering D/A-Converters without Calibration ADC. IEICE Trans. Electron. Yusuke Ikeda, Akira Matsuzawa
2007	J	`jnl`	The Effects of Switch Resistances on Pipelined ADC Performances and the Optimization for the Settling Time. IEICE Trans. Electron. Masaya Miyahara, Akira Matsuzawa
2006	J	`jnl`	Analog IC Technologies for Future Wireless Systems. IEICE Trans. Electron. Akira Matsuzawa
2006	C	`conf`	Feedforward compensation technique for all digital phase locked loop based synthesizers. ISCAS Win Chaivipas, Akira Matsuzawa, Philipus Chandra Oh
2005	J	`jnl`	A background optimization method for PLL by measuring phase jitter performance. IEEE J. Solid State Circuits Shiro Dosho, Naoshi Yanagisawa, Akira Matsuzawa
2003	J	`jnl`	A fully integrated 0.13-μm CMOS mixed-signal SoC for DVD player applications. IEEE J. Solid State Circuits Koji Okamoto, Takashi Morie, Akira Yamamoto, Kouichi Nagano, Koji Sushihara, Hiroyuki Nakahira, Ryusuke Horibe, Kazutoshi Aida, Toshihiko Takahashi, Minoru Ochiai, Akinobu Soneda, Toru Kakiage, Tamaki Iwasaki, Hiroshi Taniuchi, Tadashi Shibata, Takahiro Ochi, Masao Takiguchi, Takashi Yamamoto, Tadayoshi Seike, Akira Matsuzawa
2003	—	`conf`	Driving the SoC developments for digital consumer electronics. ESTIMedia Akira Matsuzawa
2003	A*	`conf`	How to make efficient communication, collaboration, and optimization from system to chip. DAC Akira Matsuzawa
2002	J	`jnl`	Low-power motion vector estimation using iterative search block-matching methods and a high-speed non-destructive CMOS image sensor. IEEE Trans. Circuits Syst. Video Technol. Dwi Handoko, Shoji Kawahito, Yoshiaki Tadokoro, Akira Matsuzawa
2001	J	`jnl`	A mixed-signal 0.18-μm CMOS SoC for DVD systems with 432-MSample/s PRML read channel and 16-Mb embedded DRAM. IEEE J. Solid State Circuits Takashi Yamamoto, Shin-Ichi Gotoh, Toshihiko Takahashi, Kozo Irie, Kazuya Ohshima, Nobuhiro Mimura, Kazutoshi Aida, Toshinori Maeda, Koji Sushihara, Yoichi Okamoto, Yasuhiro Tai, Makoto Usui, Takeshi Nakajima, Takahiro Ochi, Katsuhiko Komichi, Akira Matsuzawa
2001	—	`conf`	High Quality Analog CMOS and Mixed Signal LSI Design. ISQED Akira Matsuzawa
2000	J	`jnl`	A CMOS Image Sensor with Non-Destructive High-Speed Imaging Mode and Its Applications. J. Robotics Mechatronics Dwi Handoko, Shoji Kawahito, Minoru Kumahara, Nobuhiro Kawai, Yoshiaki Tadokoro, Akira Matsuzawa
1998	—	`conf`	A CMOS Smart Image Sensor LSI for Focal-Plane Compression. ASP-DAC Shoji Kawahito, Makoto Yoshida, Masaaki Sasaki, Daisuke Miyazaki, Yoshiaki Tadokoro, Kenji Murata, Shiro Doushou, Akira Matsuzawa
1998	—	`conf`	CMOS Image Sensors with Video Compression. ASP-DAC Shoji Kawahito, Yoshiaki Tadokoro, Akira Matsuzawa
1997	J	`jnl`	A 0.5 V single power supply operated high-speed boosted and offset-grounded data storage (BOGS) SRAM cell architecture. IEEE Trans. Very Large Scale Integr. Syst. Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa
1997	J	`jnl`	A CMOS image sensor with analog two-dimensional DCT-based compression circuits for one-chip cameras. IEEE J. Solid State Circuits Shoji Kawahito, Makoto Yoshida, Masaaki Sasaki, Keijiro Umehara, Daisuke Miyazaki, Yoshiaki Tadokoro, Kenji Murata, Shiro Doushou, Akira Matsuzawa
1997	A	`conf`	Design, Fabrications and Use of Mixed-Signal IC Testability Structures. ITC Kenneth P. Parker, John E. McDermid, Rodney A. Browen, Kozo Nuriya, Katsuhiro Hirayama, Akira Matsuzawa
1996	A	`conf`	A 0.5V/100 MHz over-VCC grounded data storage (OVGS) SRAM cell architecture with boosted bit-line and offset source over-driving schemes. ISLPED Hiroyuki Yamauchi, Toru Iwata, Hironori Akamatsu, Akira Matsuzawa
1996	J	`jnl`	A signal-swing suppressing strategy for power and layout area savings using time-multiplexed differential data-transfer scheme. IEEE J. Solid State Circuits Hiroyuki Yamauchi, Akira Matsuzawa
1994	J	`jnl`	Low-voltage and low-power circuit design for mixed analog/digital systems in portable equipment. IEEE J. Solid State Circuits Akira Matsuzawa
1993	J	`jnl`	A 10-b 20-MHz 30-mW pipelined interpolating CMOS ADC. IEEE J. Solid State Circuits Keiichi Kusumoto, Akira Matsuzawa, Kenji Murata
1993	J	`jnl`	A 10-b 300-MHz interpolated-parallel A/D converter. IEEE J. Solid State Circuits Hiroshi Kimura, Akira Matsuzawa, Takashi Nakamura, Shigeki Sawada