Akira Kotabe - RankMe

13 papers C 1Journal 8Unranked 4

Year	Rank	Type	Title / Venue / Authors
2012	J	`jnl`	0.5-V 25-nm 6-T Cell with Boosted Word Voltage for 1-Gb SRAMs. IEICE Trans. Electron. Akira Kotabe, Kiyoo Itoh, Riichiro Takemura
2012	J	`jnl`	A Low- IEICE Trans. Electron. Satoru Akiyama, Riichiro Takemura, Tomonori Sekiguchi, Akira Kotabe, Kiyoo Itoh
2012	J	`jnl`	Fluctuation Tolerant Charge-Integration Read Scheme for Ultrafast DNA Sequencing with Nanopore Device. IEICE Trans. Electron. Kazuo Ono, Yoshimitsu Yanagawa, Akira Kotabe, Riichiro Takemura, Tatsuo Nakagawa, Tomio Iwasaki, Takayuki Kawahara
2012	C	`conf`	Fluctuation tolerant read scheme for ultrafast DNA sequencing with nanopore device. ISCAS Yoshimitsu Yanagawa, Kazuo Ono, Akira Kotabe, Riichiro Takemura, Tatsuo Nakagawa, Tomio Iwasaki, Takayuki Kawahara
2012	J	`jnl`	Small-Sized Leakage-Controlled Gated Sense Amplifier for 0.5-V Multi-Gigabit DRAM Arrays. IEICE Trans. Electron. Akira Kotabe, Riichiro Takemura, Yoshimitsu Yanagawa, Tomonori Sekiguchi, Kiyoo Itoh
2011	J	`jnl`	1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing. IEEE J. Solid State Circuits Tomonori Sekiguchi, Kazuo Ono, Akira Kotabe, Yoshimitsu Yanagawa
2011	—	`conf`	Device-conscious circuit designs for 0.5-V high-speed memory-rich nanoscale CMOS LSIs. CICC Akira Kotabe, Kiyoo Itoh, Riichiro Takemura, Ryuta Tsuchiya, Masashi Horiguchi
2010	J	`jnl`	0.5-V Low- V IEEE J. Solid State Circuits Akira Kotabe, Yoshimitsu Yanagawa, Satoru Akiyama, Tomonori Sekiguchi
2009	—	`conf`	Low-Vt small-offset gated preamplifier for sub-1V gigabit DRAM arrays. ISSCC Satoru Akiyama, Tomonori Sekiguchi, Riichiro Takemura, Akira Kotabe, Kiyoo Itoh
2007	—	`conf`	A 512kB Embedded Phase Change Memory with 416kB/s Write Throughput at 100μA Cell Write Current. ISSCC Satoru Hanzawa, Naoki Kitai, Kenichi Osada, Akira Kotabe, Yuichi Matsui, Nozomu Matsuzaki, Norikatsu Takaura, Masahiro Moniwa, Takayuki Kawahara
2007	J	`jnl`	Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node. IEEE J. Solid State Circuits Hideaki Kurata, Kazuo Otsuga, Akira Kotabe, Shinya Kajiyama, Taro Osabe, Yoshitaka Sasago, Shunichi Narumi, Kenji Tokami, Shiro Kamohara, Osamu Tsuchiya
2005	J	`jnl`	A low-power four-transistor SRAM cell with a stacked vertical poly-silicon PMOS and a dual-word-voltage scheme. IEEE J. Solid State Circuits Akira Kotabe, Kenichi Osada, Naoki Kitai, Mio Fujioka, Shiro Kamohara, Masahiro Moniwa, Sadayuki Morita, Yoshikazu Saitoh
2001	—	`conf`	A fast motion estimation algorithm and low-power 0.13-um CMOS motion estimation circuits. ISCAS (2) Tadayoshi Enomoto, Akira Kotabe