Akihiko Yamada

28 papers A* 8A 2Journal 11Unranked 7
YearRankTypeTitle / Venue / Authors
2025 J jnl
Practical Uplink Multi-User MIMO Scheduling Based on Iterative Heuristic Search.
IEICE Trans. Commun.
Satoshi Denno, Akihiko Yamada, Yafei Hou
2023 — conf
Iterative User Scheduling Method for MU-MIMO-OFDM Systems.
GCCE
Akihiko Yamada, Satoshi Denno, Yafei Hou
2019 J jnl
2018 NEC C&C Prize Ceremony.
IEEE Ann. Hist. Comput.
Akihiko Yamada
2019 J jnl
Parametron and Relay Computers Exhibition Held at Tokyo University of Science in November, 2018.
IEEE Ann. Hist. Comput.
Akihiko Yamada
2019 — conf
Remarks on the Design of First Digital Computers in Japan - Contributions of Yasuo Komamiya.
EUROCAST (1)
Radomir S. Stankovic, Tsutomu Sasao, Jaakko T. Astola, Akihiko Yamada
2018 J jnl
IPSJ Certifies 100 IP Technology Heritage Artifacts in 10 Years.
IEEE Ann. Hist. Comput.
Akihiko Yamada
2012 J jnl
Events and Sightings.
IEEE Ann. Hist. Comput.
Akihiko Yamada, Dag Spicer
2008 J jnl
Events and Sightings.
IEEE Ann. Hist. Comput.
Chigusa Kita, Thomas Haigh, Dag Spicer, Akihiko Yamada, Thomas J. Misa
2008 — conf
Robust Face Recognition Based on Modified ICA without Training Sample of Test Subjects.
IIH-MSP
Xian-Hua Han, Yen-Wei Chen, Akihiko Yamada, Hideto Fujita
2007 J jnl
Events and Sightings.
IEEE Ann. Hist. Comput.
Chigusa Kita, Dag Spicer, Anne Fitzpatrick, Akihiko Yamada
2006 J jnl
Multi-subregion-based probabilistic approach to pose-invariant face recognition.
Syst. Comput. Jpn.
Akihiko Yamada, Takeo Kanade
2003 — conf
Multi-subregion based probabilistic approach toward pose-invariant face recognition.
CIRA
Takeo Kanade, Akihiko Yamada
1999 J jnl
A design method of multidimensional linear-phase paraunitary filter banks with a lattice structure.
IEEE Trans. Signal Process.
Shogo Muramatsu, Akihiko Yamada, Hitoshi Kiya
1998 — conf
A design method OF 2-D axial-symmetric paraunitary filter banks with a lattice structure.
EUSIPCO
Shogo Muramatsu, Akihiko Yamada, Hitoshi Kiya
1996 — conf
A design method for oversampled paraunitary DFT filter banks using householder factorization.
EUSIPCO
K. Kajita, Hiroyuki Kobayashi, Shogo Muramatsu, Akihiko Yamada, Hitoshi Kiya
1990 A conf
Challenge of design and test of ultra-large-scale circuits.
ITC
Akihiko Yamada
1989 — conf
Design Automation for Large Mainframes and Supercomputers in NEC.
IFIP Congress
Akihiko Yamada
1989 J jnl
Logic simulation engines in Japan.
IEEE Des. Test
Shigeru Takasaki, Fumiyasu Hirose, Akihiko Yamada
1989 J jnl
Scan design at NEC.
IEEE Des. Test
Shigehiro Funatsu, Masato Kawai, Akihiko Yamada
1982 A* conf
MDS: An improved total system for firmware development.
MICRO
Kazutoshi Takahashi, Etsuo Takahashi, Tatsushige Bitoh, Toshinori Aoyama, Akihiko Yamada
1982 A* conf
Timing verification system based on delay time hierarchical nature.
DAC
Minoru Nomura, Shinichi Sato, Nobuo Takano, Toshinori Aoyama, Akihiko Yamada
1981 A conf
A Calculus of Testability Measure at the Functional Level.
ITC
Shigeru Takasaki, Masato Kawai, Shigehiro Funatsu, Akihiko Yamada
1981 A* conf
Design automation status in Japan.
DAC
Akihiko Yamada
1981 A* conf
Hierarchical design verification for large digital systems.
DAC
Tohru Sasaki, Akihiko Yamada, Toshinori Aoyama, Katsutoshi Hasegawa, Shunichi Kato, Shinichi Sato
1980 A* conf
MIXS: A mixed level simulator for large digital system logic verification.
DAC
Tohru Sasaki, Akihiko Yamada, Shunichi Kato, Terufumi Nakazawa, Kyoji Tomita, Nobuyoshi Nomizu
1978 A* conf
Automatic System Level Test Generation and Fault Location for Large Digital Systems.
DAC
Akihiko Yamada, Nobuo Wakatsuki, T. Fukui, Shigehiro Funatsu
1977 A* conf
Automatic test generation for large digital circuits.
DAC
Akihiko Yamada, Nobuo Wakatsuki, Hideo Shibano, Osamu Itoh, Kyoji Tomita, Shigehiro Funatsu
1974 A* conf
Microprogramming Design support System.
DAC
Akihiko Yamada, Akihiro Kawaguchi, Kazutoshi Takahashi, Shunichi Kato