Akihide Sai

29 papers A 1Journal 11Unranked 17
YearRankTypeTitle / Venue / Authors
2022 — conf
1200x84-pixels 30fps 64cc Solid-State LiDAR RX with an HV/LV transistors Hybrid Active-Quenching-SPAD Array and Background Digital PT Compensation.
VLSI Technology and Circuits
Toshiki Sugimoto, Tuan Thanh Ta, Koichi Kokubun, Satoshi Kondo, Tetsuro Itakura, Hisaaki Katagiri, Yutaka Ota, Mitsuhiro Sengoku, Honam Kwon, Keita Sasaki, Hiroshi Kubota, Kazuhiro Suzuki, Katsuyuki Kimura, Akihide Sai
2021 A conf
Through the Looking Glass: Diminishing Occlusions in Robot Vision Systems with Mirror Reflections.
IROS
Kentaro Yoshioka, Hidenori Okuni, Tuan Thanh Ta, Akihide Sai
2021 J jnl
Through the Looking Glass: Diminishing Occlusions in Robot Vision Systems with Mirror Reflections.
CoRR
Kentaro Yoshioka, Hidenori Okuni, Tuan Thanh Ta, Akihide Sai
2020 — conf
5.1 A 240×192 Pixel 10fps 70klux 225m-Range Automotive LiDAR SoC Using a 40ch 0.0036mm
ISSCC
Satoshi Kondo, Hiroshi Kubota, Hisaaki Katagiri, Yutaka Ota, Masatoshi Hirono, Tuan Thanh Ta, Hidenori Okuni, Shinichi Ohtsuka, Yoshinari Ojima, Tomohiko Sugimoto, Hirotomo Ishii, Kentaro Yoshioka, Katsuyuki Kimura, Akihide Sai, Nobu Matsumoto
2020 — conf
A 2D-SPAD Array and Read-Out AFE for Next-Generation Solid-State LiDAR.
VLSI Circuits
Tuan Thanh Ta, Hiroshi Kubota, Koichi Kokubun, Toshiki Sugimoto, Masatoshi Hirono, Mitsuhiro Sengoku, Hisaaki Katagiri, Hidenori Okuni, Satoshi Kondo, Shinichi Ohtsuka, Honam Kwon, Keita Sasaki, Yutaka Ota, Kazuhiro Suzuki, Katsuyuki Kimura, Kentaro Yoshioka, Akihide Sai, Nobu Matsumoto
2020 J jnl
An Automotive LiDAR SoC for 240 × 192-Pixel 225-m-Range Imaging With a 40-Channel 0.0036-mm
IEEE J. Solid State Circuits
Satoshi Kondo, Hiroshi Kubota, Hisaaki Katagiri, Yutaka Ota, Masatoshi Hirono, Tuan Thanh Ta, Hidenori Okuni, Shinichi Ohtsuka, Yoshinari Ojima, Tomohiko Sugimoto, Hirotomo Ishii, Kentaro Yoshioka, Katsuyuki Kimura, Akihide Sai, Nobu Matsumoto
2019 J jnl
An 8 Bit 12.4 TOPS/W Phase-Domain MAC Circuit for Energy-Constrained Deep Learning Accelerators.
IEEE J. Solid State Circuits
Yosuke Toyama, Kentaro Yoshioka, Koichiro Ban, Shigeru Maya, Akihide Sai, Kohei Onizuka
2019 J jnl
Digital Amplifier: A Power-Efficient and Process-Scaling Amplifier for Switched Capacitor Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Hiroki Ishikuro, Tetsuro Itakura
2019 — conf
Inter-Frame Smart-Accumulation Technique for Long-Range and High-Pixel Resolution LiDAR.
COOL CHIPS
Ken Tanabe, Hiroshi Kubota, Akihide Sai, Nobu Matsumoto
2018 — conf
A 12.4TOPS/W, 20% Less Gate Count Bidirectional Phase Domain MAC Circuit for DNN Inference Applications.
A-SSCC
Yosuke Toyama, Kentaro Yoshioka, Koichiro Ban, Akihide Sai, Kohei Onizuka
2018 — conf
A 15mW -105dBm Image-Sparse-Sliding-IF Receiver with Transformer-Based on-Chip Q-Enhanced RF Matching Network for a 113dB-Link-Budget BLE 5.0 TRX.
ESSCIRC
Tuan Thanh Ta, Yosuke Ogasawara, Tong Wang, Masayoshi Oshiro, Naotaka Koide, Akihide Sai, Takashi Tokairin
2018 J jnl
A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 × 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC.
IEEE J. Solid State Circuits
Kentaro Yoshioka, Hiroshi Kubota, Tomonori Fukushima, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Kaori Watanabe, Masatoshi Hirono, Yoshinari Ojima, Katsuyuki Kimura, Sohichiroh Hosoda, Yutaka Ota, Tomohiro Koizumi, Naoyuki Kawabe, Yasuhiro Ishii, Yoichiro Iwagami, Seitaro Yagi, Isao Fujisawa, Nobuo Kano, Tomohiko Sugimoto, Daisuke Kurose, Naoya Waki, Yumi Higashi, Tetsuya Nakamura, Yoshikazu Nagashima, Hirotomo Ishii, Akihide Sai, Nobu Matsumoto
2018 — conf
A 20ch TDC/ADC hybrid SoC for 240×96-pixel 10%-reflection <0.125%-precision 200m-range imaging LiDAR with smart accumulation technique.
ISSCC
Kentaro Yoshioka, Hiroshi Kubota, Tomonori Fukushima, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Kaori Watanabe, Yoshinari Ojima, Katsuyuki Kimura, Sohichiroh Hosoda, Yutaka Ota, Tomohiro Koizumi, Naoyuki Kawabe, Yasuhiro Ishii, Yoichiro Iwagami, Seitaro Yagi, Isao Fujisawa, Nobuo Kano, Tomohiro Sugimoto, Daisuke Kurose, Naoya Waki, Yumi Higashi, Tetsuya Nakamura, Yoshikazu Nagashima, Hirotomo Ishii, Akihide Sai, Nobu Matsumoto
2018 — conf
An 113DB-Link-Budget Bluetooth-5 SoC with an 8dBm 22%-Efficiency TX.
VLSI Circuits
Tong Wang, Yosuke Ogasawara, Yuki Tuda, Tuan Thanh Ta, Masayoshi Oshiro, Jun Ihara, Tatsuhiko Maruyama, Toru Hashimoto, Akihide Sai, Takashi Tokairin
2018 — conf
Data selection and de-noising based on reliability for long-range and high-pixel resolution LiDAR.
COOL CHIPS
Ken Tanabe, Hiroshi Kubota, Akihide Sai, Nobu Matsumoto
2018 — conf
PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators.
VLSI Circuits
Kentaro Yoshioka, Yosuke Toyama, Koichiro Ban, Daisuke Yashima, Shigeru Maya, Akihide Sai, Kohei Onizuka
2018 J jnl
PhaseMAC: A 14 TOPS/W 8bit GRO based Phase Domain MAC Circuit for In-Sensor-Computed Deep Learning Accelerators.
CoRR
Kentaro Yoshioka, Yosuke Toyama, Koichiro Ban, Daisuke Yashima, Shigeru Maya, Akihide Sai, Kohei Onizuka
2017 — conf
28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier technique.
ISSCC
Kentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, Sinnyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Tetsuro Itakura
2016 — conf
19.7 A 65nm CMOS ADPLL with 360µW 1.6ps-INL SS-ADC-based period-detection-free TDC.
ISSCC
Akihide Sai, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Masanori Furuta, Tetsuro Itakura
2016 — conf
26.1 A 5.5mW ADPLL-based receiver with hybrid-loop interference rejection for BLE application in 65nm CMOS.
ISSCC
Hidenori Okuni, Akihide Sai, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura
2016 J jnl
A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS.
IEEE J. Solid State Circuits
Akihide Sai, Hidenori Okuni, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura
2015 J jnl
A Wide Bandwidth Analog Baseband Circuit for 60-GHz Proximity Wireless Communication Receiver in 65-nm CMOS.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Masanori Furuta, Hidenori Okuni, Masahiro Hosoya, Akihide Sai, Junya Matsuno, Shigehito Saigusa, Tetsuro Itakura
2014 — conf
20.4 A fully integrated single-chip 60GHz CMOS transceiver with scalable power consumption for proximity wireless communication.
ISSCC
Shigehito Saigusa, Toshiya Mitomo, Hidenori Okuni, Masahiro Hosoya, Akihide Sai, Shusuke Kawai, Tong Wang, Masanori Furuta, Kei Shiraishi, Koichiro Ban, Seiichiro Horikawa, Tomoya Tandai, Ryoko Matsuo, Takeshi Tomizawa, Hiroaki Hoshino, Junya Matsuno, Yukako Tsutsumi, Ryoichi Tachibana, Osamu Watanabe, Tetsuro Itakura
2013 J jnl
Correction to "A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication".
IEEE J. Solid State Circuits
Toshiya Mitomo, Yukako Tsutsumi, Hiroaki Hoshino, Masahiro Hosoya, Tong Wang, Yuta Tsubouchi, Ryoichi Tachibana, Akihide Sai, Yuka Kobayashi, Daisuke Kurose, Tomohiko Ito, Koichiro Ban, Tomoya Tandai, Takeshi Tomizawa
2012 J jnl
A 2-Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60-GHz Short-Range Wireless Communication.
IEEE J. Solid State Circuits
Toshiya Mitomo, Yukako Tsutsumi, Hiroaki Hoshino, Masahiro Hosoya, Tong Wang, Yuta Tsubouchi, Ryoichi Tachibana, Akihide Sai, Yuka Kobayashi, Daisuke Kurose, Tomohiko Ito, Koichiro Ban, Tomoya Tandai, Takeshi Tomizawa
2012 — conf
A 2Gb/s-throughput CMOS transceiver chipset with in-package antenna for 60GHz short-range wireless communication.
ISSCC
Toshiya Mitomo, Yukako Tsutsumi, Hiroaki Hoshino, Masahiro Hosoya, Tong Wang, Yuta Tsubouchi, Ryoichi Tachibana, Akihide Sai, Yuka Kobayashi, Daisuke Kurose, Tomohiko Ito, Koichiro Ban, Tomoya Tandai, Takeshi Tomizawa
2012 — conf
A digitally stabilized type-III PLL using ring VCO with 1.01psrms integrated jitter in 65nm CMOS.
ISSCC
Akihide Sai, Yuka Kobayashi, Shigehito Saigusa, Osamu Watanabe, Tetsuro Itakura
2011 — conf
A 570fsrms integrated-jitter ring-VCO-based 1.21GHz PLL with hybrid loop.
ISSCC
Akihide Sai, Takafumi Yamaji, Tetsuro Itakura
2008 J jnl
A Low-Power Low-Noise Clock Signal Generator for Next-Generation Mobile Wireless Terminals.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci.
Akihide Sai, Daisuke Kurose, Takafumi Yamaji, Tetsuro Itakura