Akhil Garg

11 papers A 4C 2Journal 1Unranked 4
YearRankTypeTitle / Venue / Authors
2014 A conf
Efficient testing of hierarchical core-based SOCs.
ITC
Brion L. Keller, Krishna Chakravadhanula, Brian Foutz, Vivek Chickermane, Akhil Garg, Richard Schoonover, James Sage, Don Pearl, Thomas J. Snethen
2013 A conf
SmartScan - Hierarchical test compression for pin-limited low power designs.
ITC
Krishna Chakravadhanula, Vivek Chickermane, Don Pearl, Akhil Garg, R. Khurana, Subhasish Mukherjee, P. Nagaraj
2011 A conf
State of the art low capture power methodology.
ITC
Swapnil Bahl, Roberto Mattiuzzo, Shray Khullar, Akhil Garg, S. Graniello, Khader S. Abdel-Hafez, Salvatore Talluto
2010 J jnl
Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test Time.
J. Electron. Test.
Prashant Dubey, Akhil Garg, Shashank Mahajan
2008 A conf
Low Power Test.
ITC
Swapnil Bahl, Rajiv Sarkar, Akhil Garg
2008 — conf
On Chip Jitter Measurement through a High Accuracy TDC.
ISQED
Akhil Garg, Prashant Dubey
2007 C conf
Built in Defect Prognosis for Embedded Memories.
DDECS
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani
2007 C conf
GALS Based Shared Test Architecture for Embedded Memories.
ISCAS
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani
2007 — conf
Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase Prognosis.
ISVLSI
Prashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani
2006 — conf
Fuse Area Reduction Based on Quantitative Yield Analysis and Effective Chip Cost.
SoCC
Akhil Garg, Prashant Dubey
2006 — conf
Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost.
DFT
Akhil Garg, Prashant Dubey