Akashi Satoh - RankMe

75 papers A 7B 2C 17Misc 3Journal 20Unranked 26

Year	Rank	Type	Title / Venue / Authors
2022	—	`conf`	Development of Hornet Detection Camera System for Smart Beekeeping. GCCE Mitsuki Terada, Akashi Satoh
2022	—	`conf`	Non intrusive current and power factor sensor with energy harvesting for maintenance-free operation. IEEE SENSORS Takaya Yoshitake, Akashi Satoh, Shinichiro Mito
2019	—	`conf`	Fertilizer Management System for A Compact Hydroponic Planter. GCCE Kaori Uehara, Hiromichi Ikeda, Akashi Satoh
2018	—	`conf`	A Hydroponic Planter System to enable an Urban Agriculture Service Industry. GCCE Akashi Satoh
2017	—	`conf`	A compact hardware design of a sensor module for hydroponics. GCCE Tomohiro Nishimura, Yuji Okuyama, Ayaka Matsushita, Hiromichi Ikeda, Akashi Satoh
2017	—	`conf`	Security evaluation of cryptographic modules against side-channel attack using a biased data set. GCCE Masato Matsubayashi, Hendra Guntur, Akashi Satoh
2016	—	`conf`	Clock glitch generator on SAKURA-G for fault injection attack against a cryptographic circuit. GCCE Masato Matsubayashi, Akashi Satoh, Jun Ishii
2016	—	`conf`	Comparison of side-channel attack on cryptographic cirucits between old and new technology FPGAs. GCCE Yu Nomata, Masato Matsubayashi, Kohei Sawada, Akashi Satoh
2016	—	`conf`	GPGPU software implementation of authenticated encryption algorithm Minalpher. GCCE Makiko Kosugi, Akashi Satoh
2016	—	`conf`	High-accuracy and low-cost sensor module for hydroponic culture system. GCCE Tomohiro Nishimura, Yuji Okuyama, Akashi Satoh
2015	—	`conf`	FPGA implementation of authenticated encryption algorithm Minalpher. GCCE Makiko Kosug, Masahiro Yasuda, Akashi Satoh
2015	—	`conf`	Side-channel Attack user reference architecture board SAKURA-W for security evaluation of IC card. GCCE Masato Matsubayashi, Akashi Satoh
2014	J	`jnl`	Evaluation of Physical Unclonable Functions for 28-nm Process Field-Programmable Gate Arrays. J. Inf. Process. Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh, Shin-ichi Kawamura, Kazukuni Kobara
2014	—	`conf`	FPGA implementation of new standard hash function Keccak. GCCE Tatsuya Honda, Hendra Guntur, Akashi Satoh
2014	—	`conf`	Side-channel AttacK User Reference Architecture board SAKURA-G. GCCE Hendra Guntur, Jun Ishii, Akashi Satoh
2013	J	`jnl`	A Fast Power Current Simulation of Cryptographic VLSI Circuits for Side Channel Attack Evaluation. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Daisuke Fujimoto, Toshihiro Katashita, Akihiko Sasaki, Yohei Hori, Akashi Satoh, Makoto Nagata
2013	J	`jnl`	Bitstream Protection in Dynamic Partial Reconfiguration Systems Using Authenticated Encryption. IEICE Trans. Inf. Syst. Yohei Hori, Toshihiro Katashita, Hirofumi Sakane, Kenji Toda, Akashi Satoh
2012	J	`jnl`	A Configurable On-Chip Glitchy-Clock Generator for Fault Injection Experiments. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Sho Endo, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh
2012	J	`jnl`	Evaluation of Information Leakage from Cryptographic Hardware via Common-Mode Current. IEICE Trans. Electron. Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takeshi Sugawara, Yoshiki Kayano, Takafumi Aoki, Shigeki Minegishi, Akashi Satoh, Hideaki Sone, Hiroshi Inoue
2012	J	`jnl`	Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates. IEEE Trans. Very Large Scale Integr. Syst. Miroslav Knezevic, Kazuyuki Kobayashi, Jun Ikegami, Shin'ichiro Matsuo, Akashi Satoh, Ünal Koçabas, Junfeng Fan, Toshihiro Katashita, Takeshi Sugawara, Kazuo Sakiyama, Ingrid Verbauwhede, Kazuo Ohta, Naofumi Homma, Takafumi Aoki
2011	—	`conf`	A fast power current analysis methodology using capacitor charging model for side channel attack evaluation. HOST Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Akihiro T. Sasaki, Yohei Hori, Akashi Satoh
2011	J	`jnl`	An on-chip glitchy-clock generator for testing fault injection attacks. J. Cryptogr. Eng. Sho Endo, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh
2011	J	`jnl`	High-Performance Architecture for Concurrent Error Detection for AES Processors. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh
2011	—	`conf`	Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function. ReConFig Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh
2011	J	`jnl`	Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers. IEEE Trans. Very Large Scale Integr. Syst. Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh
2010	J	`jnl`	A Design Methodology for a DPA-Resistant Circuit with RSL Techniques. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Daisuke Suzuki, Minoru Saeki, Koichi Shimizu, Akashi Satoh, Tsutomu Matsumoto
2010	J	`jnl`	Comparative Power Analysis of Modular Exponentiation Algorithms. IEEE Trans. Computers Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Akashi Satoh, Adi Shamir
2010	—	`conf`	Hardware Implementations of Hash Function Luffa. HOST Akashi Satoh, Toshihiro Katashita, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki
2010	J	`jnl`	Profiling attack using multivariate regression analysis. IEICE Electron. Express Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh
2010	—	`conf`	Prototyping Platform for Performance Evaluation of SHA-3 Candidates. HOST Kazuyuki Kobayashi, Jun Ikegami, Kazuo Sakiyama, Kazuo Ohta, Miroslav Knezevic, Ünal Koçabas, Junfeng Fan, Ingrid Verbauwhede, Eric Xu Guo, Shin'ichiro Matsuo, Sinan Huang, Leyla Nazhandali, Akashi Satoh
2010	—	`conf`	Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs. ReConFig Yohei Hori, Takahiro Yoshida, Toshihiro Katashita, Akashi Satoh
2009	A	`conf`	A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques. CHES Minoru Saeki, Daisuke Suzuki, Koichi Shimizu, Akashi Satoh
2009	C	`conf`	Compact and High-speed Hardware Architectures for Hash Function Tiger. ISCAS Akashi Satoh, Nicolas Sklavos
2009	—	`conf`	Development of side-channel attack standard evaluation environment. ECCTD Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki
2009	—	`conf`	Differential power analysis of AES ASIC implementations with various S-box circuits. ECCTD Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh
2009	C	`conf`	Evaluation of Simple/Comparative Power Analysis against an RSA ASIC Implementation. ISCAS Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh
2009	J	`jnl`	High-Performance Hardware Architectures for Galois Counter Mode. IEEE Trans. Computers Akashi Satoh, Takeshi Sugawara, Takafumi Aoki
2009	—	`conf`	Is the differential frequency-based attack effective against random delay insertion? SiPS Yingxi Lu, Keanhong Boey, Máire O'Neill, John V. McCanny, Akashi Satoh
2009	Misc	`conf`	Mechanism behind Information Leakage in Electromagnetic Analysis of Cryptographic Modules. WISA Takeshi Sugawara, Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone, Akashi Satoh
2008	J	`jnl`	A High-Resolution Phase-Based Waveform Matching and Its Application to Side-Channel Attacks. IEICE Trans. Fundam. Electron. Commun. Comput. Sci. Naofumi Homma, Sei Nagashima, Takeshi Sugawara, Takafumi Aoki, Akashi Satoh
2008	C	`conf`	ASIC hardware implementations for 512-bit hash function Whirlpool. ISCAS Akashi Satoh
2008	Misc	`conf`	Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems. IWSEC Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda
2008	B	`conf`	Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems. FPL Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda
2008	B	`conf`	Chosen-message SPA attacks against FPGA-based RSA hardware implementations. FPL Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh
2008	A	`conf`	Collision-Based Power Analysis of Modular Exponentiation Using Chosen-Message Pairs. CHES Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Akashi Satoh, Adi Shamir
2008	Misc	`conf`	Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool. WISA Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh
2008	—	`conf`	Enhanced Correlation Power Analysis Using Key Screening Technique. ReConFig Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki
2008	C	`conf`	Enhanced power analysis attack using chosen message against RSA hardware implementations. ISCAS Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh
2008	A	`conf`	High-Performance Concurrent Error Detection Scheme for AES Hardware. CHES Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki
2008	C	`conf`	High-performance ASIC implementations of the 128-bit block cipher CLEFIA. ISCAS Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh
2008	C	`conf`	Systematic design of high-radix Montgomery multipliers for RSA processors. ICCD Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh
2007	C	`conf`	A High-Performance ASIC Implementation of the 64-bit Block Cipher CAST-128. ISCAS Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh
2007	J	`jnl`	ASIC-hardware-focused comparison for hash functions MD5, RIPEMD-160, and SHS. Integr. Akashi Satoh, Tadanobu Inoue
2007	C	`conf`	DPA Using Phase-Based Waveform Matching against Random-Delay Countermeasure. ISCAS Sei Nagashima, Naofumi Homma, Yuichi Imai, Takafumi Aoki, Akashi Satoh
2007	C	`conf`	High-Speed Parallel Hardware Architecture for Galois Counter Mode. ISCAS Akashi Satoh
2007	C	`conf`	High-Speed Pipelined Hardware Architecture for Galois Counter Mode. ISC Akashi Satoh, Takeshi Sugawara, Takafumi Aoki
2007	C	`conf`	SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier. ISCAS Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh
2006	A	`conf`	High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching. CHES Naofumi Homma, Sei Nagashima, Yuichi Imai, Takafumi Aoki, Akashi Satoh
2006	C	`conf`	High-speed hardware architectures for authenticated encryption mode GCM. ISCAS Akashi Satoh
2005	—	`conf`	ASIC-Hardware-Focused Comparison for Hash Functions MD5, RIPEMD-160, and SHS. ITCC (1) Akashi Satoh, Tadanobu Inoue
2005	C	`conf`	Hardware Architecture and Cost Estimates for Breaking SHA-1. ISC Akashi Satoh
2004	J	`jnl`	A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. IEEE Trans. Very Large Scale Integr. Syst. Sumio Morioka, Akashi Satoh
2004	J	`jnl`	On-demand design service innovations. IBM J. Res. Dev. Shigenori Shimizu, Hiroshi Ishikawa, Akashi Satoh, Toru Aihara
2003	J	`jnl`	A Scalable Dual-Field Elliptic Curve Cryptographic Processor. IEEE Trans. Computers Akashi Satoh, Kohji Takano
2003	C	`conf`	Hardware-Focused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES. ISC Akashi Satoh, Sumio Morioka
2003	A	`conf`	Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia. CHES Akashi Satoh, Sumio Morioka
2002	C	`conf`	A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture. ICCD Sumio Morioka, Akashi Satoh
2002	A	`conf`	An Optimized S-Box Circuit Architecture for Low Power AES Design. CHES Sumio Morioka, Akashi Satoh
2002	C	`conf`	Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI. ISC Akashi Satoh, Sumio Morioka
2001	A	`conf`	A Compact Rijndael Hardware Architecture with S-Box Optimization. ASIACRYPT Akashi Satoh, Sumio Morioka, Kohji Takano, Seiji Munetoh
2000	—	`conf`	High-Speed MARS Hardware. AES Candidate Conference Akashi Satoh, Nobuyuki Ooba, Kohji Takano, Edward D'Avignon
1997	—	`conf`	A High-Speed Small RSA Encryption LSI with Low Power Dissipation. ISW Akashi Satoh, Yoshinao Kobayashi, Hideto Niijima, Nobuyuki Ooba, Seiji Munetoh, Sadamichi Sone
1997	C	`conf`	Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. ICCD W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, Toshiaki Kirihata, Akashi Satoh, Seiji Munetoh, Hing Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi
1992	J	`jnl`	A 14-ns 14-Mb CMOS DRAM with 300-mW active power. IEEE J. Solid State Circuits Toshiaki Kirihata, Sang H. Dhong, Koji Kitamura, Toshio Sunaga, Yasunao Katayama, Roy E. Scheuerlein, Akashi Satoh, Yoshinori Sakaue, Kentaroh Tobimatsu, Koji Hosokawa, Takaki Saitoh, Takefumi Yoshikawa, Hideki Hashimoto, Michiya Kazusawa
1992	J	`jnl`	A pulsed sensing scheme with a limited bit-line swing. IEEE J. Solid State Circuits Roy E. Scheuerlein, Yasunao Katayama, Toshiaki Kirihata, Yoshinori Sakaue, Akashi Satoh, Toshio Sunaga, T. Yoshikawa, Koji Kitamura, Sang H. Dhong