Ajith Pasqual

22 papers A 2B 1C 3Misc 1Journal 4Unranked 11
YearRankTypeTitle / Venue / Authors
2025 C conf
End-to-End Wrist PPG Generation Using Radial Artery Hemodynamics and Light Transport Simulation.
BIBE
Supun Kuruppu, Biyon Fernando, Dakshina Tharindu, Dumindu Bandara, Ajith Pasqual
2022 J jnl
A Four-Step Method to Synthesize a DC-DC Converter for Multi-Inductor Realizable Arbitrary Voltage Conversion Ratio.
IEEE Trans. Ind. Electron.
Thilina S. Ambagahawaththa, Dulika Nayanasiri, Ajith Pasqual
2021 J jnl
Reconfigurable co-processor architecture with limited numerical precision to accelerate deep convolutional neural networks.
CoRR
Sasindu Wijeratne, Sandaruwan Jayaweera, Mahesh Dananjaya, Ajith Pasqual
2019 — conf
FPGA IP for Real-time 4K HDR Image Decoding in VR Devices.
LASCAS
Kamlakannan Kamalavasan, Ratnasegar Natheesan, Kathirgamaraja Pradeep, Sivakumaran Gowthaman, Sivakaneshan Aravinth, Ajith Pasqual
2019 — conf
SMPTE ST 2110 Compliant Scalable Architecture on FPGA for end to end Uncompressed Professional Video Transport Over IP Networks.
ASAP
Nisal Ranasinghe, Ravindu Bangamuarachchi, Jayath Seneviratne, Achini Jayawardane, Ajith Pasqual, R. M. A. U. Senarath
2019 A conf
Scalable High Performance SDN Switch Architecture on FPGA for Core Networks.
FPGA
Sasindu Wijeratne, Ashen Ekanayake, Sandaruwan Jayaweera, Danuka Ravishan, Ajith Pasqual
2019 J jnl
Scalable High Performance SDN Switch Architecture on FPGA for Core Networks.
CoRR
Sasindu Wijeratne, Ashen Ekanayake, Sandaruwan Jayaweera, Danuka Ravishan, Ajith Pasqual
2018 C conf
A Novel Low-Complexity VLSI Architecture for an EEG Feature Extraction Platform.
DSD
Dakila Serasinghe, Duvindu Piyasena, Ajith Pasqual
2018 — conf
EdgeNet: SqueezeNet like Convolution Neural Network on Embedded FPGA.
ICECS
Kathirgamaraja Pradeep, Kamalakkannan Kamalavasan, Ratnasegar Natheesan, Ajith Pasqual
2018 — conf
Reconfigurable Co-Processor Architecture with Limited Numerical Precision to Accelerate Deep Convolutiosnal Neural Networks.
ASAP
Sasindu Wijeratne, Sandaruwan Jayaweera, Mahesh Dananjaya, Ajith Pasqual
2017 A conf
FPAA and FPGA based universal sensor node design.
ICST
Ayanga D. Kalupahana, Nisal Hemadasa, Nipun Wijerathne, Anuranga Ranasinghe, Ajith Pasqual
2017 — conf
High performance hardware architectures for Intra Block Copy and Palette Coding for HEVC screen content coding extension.
ASAP
Rishan Senanayake, Namitha Liyanage, Sasindu Wijeratne, Sachille Atapattu, Kasun Athukorala, P. M. K. Tharaka, Geethan Karunaratne, R. M. A. U. Senarath, Ishantha Perera, Ashen Ekanayake, Ajith Pasqual
2017 — conf
Hybrid Software Defined Networking Controller.
DCNET
Kosala Perera, Udesh Gunarathne, Binal Chathuranga, Chamika Ramanayake, Ajith Pasqual
2017 — conf
Runtime rule-reconfigurable high throughput NIPS on FPGA.
FPT
P. M. K. Tharaka, D. M. D. Wijerathne, Navoda Perera, Dinushan Vishwajith, Ajith Pasqual
2016 J jnl
4K Real-Time HEVC Decoder on an FPGA.
IEEE Trans. Circuits Syst. Video Technol.
Maleen Abeydeera, Manupa Karunaratne, Geethan Karunaratne, Kalana De Silva, Ajith Pasqual
2016 — conf
High performance flow matching architecture for OpenFlow data plane.
NFV-SDN
Viduranga Bandara Wijekoon, T. M. Dananjaya, P. H. Kariyawasam, S. Iddamalgoda, Ajith Pasqual
2016 — conf
Real time all intra HEVC HD encoder on FPGA.
ASAP
Sachille Atapattu, Namitha Liyanage, Nisal Menuka, Ishantha Perera, Ajith Pasqual
2015 B conf
HEVC inverse transform architecture utilizing coefficient sparsity.
ICIP
Maleen Abeydeera, Ajith Pasqual
2012 — conf
High performance parallel packet Classification architecture with Popular Rule Caching.
ICON
Samoda Gamage, Ajith Pasqual
2008 C conf
Impact of ICT on learning and teaching.
ISTAS
Ravina Panangalage, Ajith Pasqual
1999 — conf
Software Based Object Tracking with Visual Feature Integration.
ICIP (2)
Ajith Pasqual, Hidenori Takeshima, Kiyoharu Aizawa
1998 Misc conf
Selection/Substitution of Visual Features for Object Tracking.
MVA
Ajith Pasqual, Kiyoharu Aizawa, Mitsutoshi Hatori