Ajith Amerasekera

14 papers A 2Misc 1Journal 3Unranked 8
YearRankTypeTitle / Venue / Authors
2016 — conf
Session 3 overview: Ultra-high-speed wireline transceivers and energy-efficient links.
ISSCC
Hyeon-Min Bae, Ajith Amerasekera
2015 — conf
Session 10 overview: Advanced wireline techniques and PLLs: Wireline subcommittee.
ISSCC
Gerrit den Besten, Ajith Amerasekera
2014 J jnl
A 3.4-pJ FeRAM-Enabled D Flip-Flop in 0.13-µm CMOS for Nonvolatile Processing in Digital Systems.
IEEE J. Solid State Circuits
Masood Qazi, Ajith Amerasekera, Anantha P. Chandrakasan
2014 — conf
ES2: Data centers to support tomorrow's cloud.
ISSCC
Leland Chang, Ajith Amerasekera, Takashi Hashimoto
2013 — conf
A 3.4pJ FeRAM-enabled D flip-flop in 0.13µm CMOS for nonvolatile processing in digital systems.
ISSCC
Masood Qazi, Ajith Amerasekera, Anantha P. Chandrakasan
2013 — conf
ES3: High-speed communications on 4 wheels: What's in your next car?
ISSCC
Nicola Da Dalt, Ajith Amerasekera
2012 — conf
Foreword.
VLSIC
Ajith Amerasekera, Makoto Nagata
2012 A ed.
International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, USA - July 30 - August 01, 2012
ISLPED
Naresh R. Shanbhag, Massimo Poncino, Pai H. Chou, Ajith Amerasekera
2010 A conf
Ultra low power electronics in the next decade.
ISLPED
Ajith Amerasekera
2008 J jnl
The Changing Design Landscape.
IEEE Des. Test Comput.
Ajith Amerasekera
2007 — conf
A 12.5Gb/s SerDes in 65nm CMOS Using a Baud-Rate ADC with Digital Receiver Equalization and Clock Recovery.
ISSCC
Mike Harwood, Nirmal Warke, Richard Simpson, Tom Leslie, Ajith Amerasekera, Sean Batty, Derek Colman, Eugenia Carr, Venu Gopinathan, Steve Hubbins, Peter Hunt, Andy Joy, Pulkit Khandelwal, Bob Killips, Thomas Krause, Shaun Lytollis, Andy Pickering, Mark Saxton, David Sebastio, Graeme Swanson, Andre Szczepanek, Terry Ward, Jeff Williams, Richard Williams, Tom Willwerth
2007 Misc conf
Concurrent Optimization of Technology and Design for Nano CMOS.
VLSI Design
Ajith Amerasekera
2002 — conf
A Robust Digital Delay Line Architecture in a 0.13µm CMOS Technology Node for Reduced Design and Process Sensitivities.
ISQED
Prasun Raha, Scott Randall, Richard Jennings, Bob Helmick, Ajith Amerasekera, Baher Haroun
1993 J jnl
ESD: a pervasive reliability concern for IC technologies.
Proc. IEEE
Charvaka Duvvury, Ajith Amerasekera