Ajit Pal

51 papers A* 1C 1Misc 16Journal 16Unranked 15
YearRankTypeTitle / Venue / Authors
2016 J jnl
Extending light-trail into elastic optical networks for dynamic traffic grooming.
Opt. Switch. Netw.
Prasanta Majumdar, Ajit Pal, Tanmay De
2015 J jnl
A load balanced approach of multicast routing and wavelength assignment in WDM networks.
Int. J. Commun. Networks Distributed Syst.
Subhendu Barat, Ajit Pal, Tanmay De
2015 J jnl
Energy Efficient Array Computations Using Loop Unrolling with Partial Gray Code Sequence.
J. Low Power Electron.
Sumanta Pyne, Ajit Pal
2015 J jnl
Runtime Leakage Power Reduction Using Loop Unrolling and Fine Grained Power Gating.
J. Low Power Electron.
Sumanta Pyne, Ajit Pal
2014 — conf
Loop unrolling with fine grained power gating for runtime leakage power reduction.
VDAT
Sumanta Pyne, Ajit Pal
2013 J jnl
A Multi-objective Perspective for Operator Scheduling using Fine-grained DVS Architecture
CoRR
Rajdeep Mukherjee, Priyankar Ghosh, Pallab Dasgupta, Ajit Pal
2013 J jnl
An Integrated Approach for Fine-Grained Power and Peak Temperature Management During High-Level Synthesis.
J. Low Power Electron.
Rajdeep Mukherjee, Priyankar Ghosh, Pallab Dasgupta, Ajit Pal
2013 — conf
Energy Efficient Array Initialization Using Loop Unrolling with Partial Gray Code Sequence.
VDAT
Sumanta Pyne, Ajit Pal
2013 J jnl
Formal Verification of Architectural Power Intent.
IEEE Trans. Very Large Scale Integr. Syst.
Aritra Hazra, Sahil Goyal, Pallab Dasgupta, Ajit Pal
2013 Misc conf
Formal Verification of Hardware / Software Power Management Strategies.
VLSI Design
Rajdeep Mukherjee, Pallab Dasgupta, Ajit Pal, Subhankar Mukherjee
2013 — book
Impact of Leakage Power Reduction Techniques on Parametric Yield - Low-Power Design of Digital Integrated Circuits under Process Parameter Variations.
Sudip Roy, Ajit Pal
2013 J jnl
POWER-TRUCTOR: An Integrated Tool Flow for Formal Verification and Coverage of Architectural Power Intent.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Aritra Hazra, Rajdeep Mukherjee, Pallab Dasgupta, Ajit Pal, Kevin Harer, Ansuman Banerjee, Subhankar Mukherjee
2012 J jnl
Branch Target Buffer Energy Reduction Through Efficient Multiway Branch Translation Techniques.
J. Low Power Electron.
Sumanta Pyne, Ajit Pal
2012 — conf
Multi-objective Low-Power CDFG Scheduling Using Fine-Grained DVS Architecture in Distributed Framework.
ISED
Rajdeep Mukherjee, Priyankar Ghosh, N. Sravan Kumar, Pallab Dasgupta, Ajit Pal
2012 — conf
Operator Scheduling Revisited: A Multi-objective Perspective for Fine-Grained DVS Architecture.
ACITY (3)
Rajdeep Mukherjee, Priyankar Ghosh, Pallab Dasgupta, Ajit Pal
2011 Misc conf
An Algorithm for Traffic Grooming in WDM Mesh Networks Using Dynamic Path Selection Strategy.
ICDCN
Sukanta Bhattacharya, Tanmay De, Ajit Pal
2011 J jnl
Distributed dynamic grooming routing and wavelength assignment in WDM optical mesh networks.
Photonic Netw. Commun.
Tanmay De, Puneet Jain, Ajit Pal
2011 — conf
Low-Power, Energy-Efficient Full Adder for Deep-Submicron Design.
ISVLSI
Mallikarjuna Rao Nimmagadda, Ajit Pal
2010 J jnl
A New Technique for Runtime Leakage Reduction and Its Sensitivity and Parametric Yield Analysis Under Effective Channel-Length Variation.
J. Low Power Electron.
Sudip Roy, Ajit Pal
2010 Misc conf
Credit Reputation Propagation: A Strategy to Curb Free-Riding in a Large BitTorrent Swarm.
ICDCN
Suman Paul, Subrata Nandi, Ajit Pal
2010 A* conf
Leveraging UPF-extracted assertions for modeling and formal verification of architectural power intent.
DAC
Aritra Hazra, Srobona Mitra, Pallab Dasgupta, Ajit Pal, Debabrata Bagchi, Kaustav Guha
2010 — conf
Traffic grooming in WDM mesh networks using dynamic path selection strategy.
WOCN
Sukanta Bhattacharya, Tanmay De, Ajit Pal
2010 J jnl
Traffic grooming, routing, and wavelength assignment in an optical WDM mesh networks based on clique partitioning.
Photonic Netw. Commun.
Tanmay De, Ajit Pal, Indranil Sengupta
2009 Misc conf
Synthesis & Testing for Low Power.
VLSI Design
Ajit Pal, Santanu Chattopadhyay
2008 — conf
A Multi Objective Evolutionary Algorithm Based Approach for Traffic Grooming, Routing and Wavelength Assignment in Optical WDM Networks.
ICIIS
Tanmay De, Puneet Jain, Ajit Pal, Indranil Sengupta
2008 — conf
A genetic algorithm based approach for traffic grooming, routing and wavelength assignment in optical WDM mesh networks.
ICON
Tanmay De, Puneet Jain, Ajit Pal, Indranil Sengupta
2008 — conf
A power-aware wireless sensor network based bridge monitoring system.
ICON
Sujan Kundu, Sudip Roy, Ajit Pal
2008 Misc conf
Routing and Wavelength Assignment in All Optical Networks Based on Clique Partitioning.
ICDCN
Tanmay De, Ajit Pal, Indranil Sengupta
2008 C conf
Why to Use Dual-Vt, If Single-Vt Serves the Purpose Better under Process Parameter Variations?
DSD
Sudip Roy, Ajit Pal
2007 Misc conf
Low Power Sensor Node for a Wireless Sensor Network.
VLSI Design
Akepati Sravan, Sujan Kundu, Ajit Pal
2006 — conf
Low Power BDD-based Synthesis Using Dual Rail Static DCVSPG Logic.
APCCAS
Gopal Paul, Sambhu Nath Pradhan, Ajit Pal, Bhargab B. Bhattacharya
2006 — conf
On finding the minimum test set of a BDD-based circuit.
ACM Great Lakes Symposium on VLSI
Gopal Paul, Ajit Pal, Bhargab B. Bhattacharya
2005 — ed.
Distributed Computing - IWDC 2005, 7th International Workshop, Kharagpur, India, December 27-30, 2005, Proceedings
IWDC
Ajit Pal, Ajay D. Kshemkalyani, Rajeev Kumar, Arobinda Gupta
2004 Misc conf
Energy-aware Logic Synthesis and Technology Mapping for MUX-based FPGAs.
VLSI Design
Maitrali Marik, Ajit Pal
2004 — conf
Routing and Wavelength Assignment in Wavelength Division Multiplexing Networks.
IWDC
Ajit Pal, Umesh Patel
2004 Misc conf
Synthesis of Low Power High Performance Dual-VT PTL Circuits.
VLSI Design
Debasis Samanta, Ajit Pal
2003 Misc conf
Synthesis of Dual-VT Dynamic CMOS Circuits.
VLSI Design
Debasis Samanta, Ajit Pal
2003 — conf
Synthesis of high performance low power PTL circuits.
ASP-DAC
Debasis Samanta, M. C. Dharmadeep, Ajit Pal
2002 — conf
Optimal Dual -VT Assignment for Low-Voltage Energy-Constrained CMOS Circuits.
ASP-DAC/VLSI Design
Debasis Samanta, Ajit Pal
2002 — conf
Synthesis of High Performance Low Power Dynamic CMOS Circuits.
ASP-DAC/VLSI Design
Debasis Samanta, Nishant Sinha, Ajit Pal
2001 Misc conf
Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits.
VLSI Design
Nikhil Tripathi, Amit M. Bhosle, Debasis Samanta, Ajit Pal
1999 Misc conf
Deadline Assignment in Multiprocessor-Based Fault-Tolerant Systems.
HiPC
Sharath Kumar Kodase, N. V. Satyanarayana, Ajit Pal, Rajib Mall
1998 J jnl
An algorithm for finding a non-trivial lower bound for channel routing1.
Integr.
Rajat Kumar Pal, Sudebkumar Prasant Pal, Ajit Pal
1998 J jnl
DDSCHED: A distributed dynamic real-time scheduling algorithm.
Parallel Distributed Comput. Pract.
Anup K. Bhattacharjee, K. Ravindranath, Ajit Pal, Rajib Mall
1997 Misc conf
An Algorithm for Finding a Non-Trivial Lower Bound for Channel Routing.
VLSI Design
Rajat Kumar Pal, Sudebkumar Prasant Pal, Ajit Pal
1996 J jnl
A layered architecture for real-time systems.
Microprocess. Microsystems
N. V. Satyanarayana, Rajib Mall, Ajit Pal
1995 Misc conf
A general graph theoretic framework for multi-layer channel routing.
VLSI Design
Rajat Kumar Pal, A. K. Datta, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal
1995 Misc conf
Computing area and wire length efficient routes for channels.
VLSI Design
Rajat Kumar Pal, Sudebkumar Prasant Pal, M. M. Das, Ajit Pal
1993 Misc conf
NP-Completeness of Multi-Layer No-Dogleg Channel Routing and an Efficient Heuristic.
VLSI Design
Rajat Kumar Pal, Sudebkumar Prasant Pal, Ajit Pal, Alak K. Dutta
1992 Misc conf
An Efficient Graph-Theoretic Algorithm for Three-Layer Channel Routing.
VLSI Design
Rajat Kumar Pal, Ajit Pal
1986 J jnl
An Algorithm for Optimal Logic Design Using Multiplexers.
IEEE Trans. Computers
Ajit Pal