Ajay N. Bhoj

13 papers C 1Misc 1Journal 7Unranked 3
YearRankTypeTitle / Venue / Authors
2016 Misc conf
Fast FinFET Device Simulation under Process-Voltage Variations Using an Assisted Speed-Up Mechanism.
VLSID
Sourindra Chaudhuri, Ajay N. Bhoj, Debajit Bhattacharya, Niraj K. Jha
2015 J jnl
Design of Efficient Content Addressable Memories in High-Performance FinFET Technology.
IEEE Trans. Very Large Scale Integr. Syst.
Debajit Bhattacharya, Ajay N. Bhoj, Niraj K. Jha
2015 J jnl
Super Fast Physics-Based Methodology for Accurate Memory Yield Prediction.
IEEE Trans. Very Large Scale Integr. Syst.
Rajiv V. Joshi, Keunwoo Kim, Rouwaida Kanj, Ajay N. Bhoj, Matthew M. Ziegler, Phil Oldiges, Pranita Kerber, Robert Wong, Terence Hook, Sudesh Saroop, Carl Radens, Chun-Chen Yeh
2014 J jnl
Parasitics-Aware Design of Symmetric and Asymmetric Gate-Workfunction FinFET SRAMs.
IEEE Trans. Very Large Scale Integr. Syst.
Ajay N. Bhoj, Niraj K. Jha
2013 J jnl
3-D-TCAD-Based Parasitic Capacitance Extraction for Emerging Multigate Devices and Circuits.
IEEE Trans. Very Large Scale Integr. Syst.
Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha
2013 J jnl
Design of Logic Gates and Flip-Flops in High-Performance FinFET Technology.
IEEE Trans. Very Large Scale Integr. Syst.
Ajay N. Bhoj, Niraj K. Jha
2013 — —
Device-circuit co-design approaches for Multi-gate FET technologies.
Ajay N. Bhoj
2013 J jnl
Efficient Methodologies for 3-D TCAD Modeling of Emerging Devices and Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ajay N. Bhoj, Rajiv V. Joshi, Niraj K. Jha
2011 — conf
Design of ultra-low-leakage logic gates and flip-flops in high-performance FinFET technology.
ISQED
Ajay N. Bhoj, Niraj K. Jha
2010 — conf
Die-level leakage power analysis of FinFET circuits considering process variations.
ISQED
Prateek Mishra, Ajay N. Bhoj, Niraj K. Jha
2010 — conf
Fault modeling for FinFET circuits.
NANOARCH
Muzaffer O. Simsir, Ajay N. Bhoj, Niraj K. Jha
2010 J jnl
Gated-diode FinFET DRAMs: Device and circuit design-considerations.
ACM J. Emerg. Technol. Comput. Syst.
Ajay N. Bhoj, Niraj K. Jha
2009 C conf
Pragmatic design of gated-diode FinFET DRAMs.
ICCD
Ajay N. Bhoj, Niraj K. Jha