Ajay Kumar Verma

29 papers A* 3A 7B 1C 1Misc 2Journal 7Unranked 7
YearRankTypeTitle / Venue / Authors
2021 J jnl
Deep learning based network similarity for model selection.
Data Sci.
Kushal Veer Singh, Ajay Kumar Verma, Lovekesh Vig
2012 — conf
Document image binarization using wavelets for OCR applications.
ICVGIP
C. Patvardhan, Ajay Kumar Verma, C. Vasantha Lakshmi
2010 J jnl
An Optimal Linear-Time Algorithm for Interprocedural Register Allocation in High Level Synthesis Using SSA Form.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Philip Brisk, Ajay Kumar Verma, Paolo Ienne
2010 J jnl
Fast, Nearly Optimal ISE Identification With I/O Serialization Through Maximal Clique Enumeration.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2010 — conf
Generating Distributed Query Processing Plans Using Genetic Algorithm.
DSDE
T. V. Vijay Kumar, Vikram Singh, Ajay Kumar Verma
2010 J jnl
Improving FPGA Performance for Carry-Save Arithmetic.
IEEE Trans. Very Large Scale Integr. Syst.
Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2010 — —
Pre-Synthesis Optimization of Arithmetic Circuits.
Ajay Kumar Verma
2010 B conf
Synthesis of Floating-Point Addition Clusters on FPGAs Using Carry-Save Arithmetic.
FPL
Amit Verma, Ajay Kumar Verma, Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne
2009 — conf
Arithmetic optimization for custom instruction set synthesis.
SASP
Ajay Kumar Verma, Yi Zhu, Philip Brisk, Paolo Ienne
2009 C conf
Challenges in Automatic Optimization of Arithmetic Circuits.
IEEE Symposium on Computer Arithmetic
Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2009 J jnl
Field Programmable Compressor Trees: Acceleration of Multi-Input Addition on FPGAs.
ACM Trans. Reconfigurable Technol. Syst.
Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Seyed-Hosein Attarzadeh-Niaki, Chrysostomos Nicopoulos, Frank K. Gürkaynak, Philip Brisk, Yusuf Leblebici, Paolo Ienne
2009 — conf
Hybrid LZA: a near optimal implementation of the leading zero anticipator.
ASP-DAC
Amit Verma, Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2009 A conf
Iterative layering: Optimizing arithmetic circuits by structuring the information flow.
ICCAD
Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2009 J jnl
Optimistic chordal coloring: a coalescing heuristic for SSA form programs.
Des. Autom. Embed. Syst.
Philip Brisk, Ajay Kumar Verma, Paolo Ienne
2008 A conf
Architectural improvements for field programmable counter arrays: enabling efficient synthesis of fast compressor trees on FPGAs.
FPGA
Alessandro Cevrero, Panagiotis Athanasopoulos, Hadi Parandeh-Afshar, Ajay Kumar Verma, Philip Brisk, Frank K. Gürkaynak, Yusuf Leblebici, Paolo Ienne
2008 J jnl
Data-Flow Transformations to Maximize the Use of Carry-Save Representation in Arithmetic Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2008 — conf
Fast, quasi-optimal, and pipelined instruction-set extensions.
ASP-DAC
Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2008 A conf
Variable Latency Speculative Addition: A New Paradigm for Arithmetic Circuit Design.
DATE
Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2007 Misc conf
An optimistic and conservative register assignment heuristic for chordal graphs.
CASES
Philip Brisk, Ajay Kumar Verma, Paolo Ienne
2007 A conf
Automatic synthesis of compressor trees: reevaluating large counters.
DATE
Ajay Kumar Verma, Paolo Ienne
2007 A* conf
Enhancing FPGA Performance for Arithmetic Circuits.
DAC
Philip Brisk, Ajay Kumar Verma, Paolo Ienne, Hadi Parandeh-Afshar
2007 — conf
Improving XOR-Dominated Circuits by Exploiting Dependencies between Operands.
ASP-DAC
Ajay Kumar Verma, Paolo Ienne
2007 A conf
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design.
ICCAD
Philip Brisk, Ajay Kumar Verma, Paolo Ienne
2007 A* conf
Progressive Decomposition: A Heuristic to Structure Arithmetic Circuits.
DAC
Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2007 Misc conf
Rethinking custom ISE identification: a new processor-agnostic method.
CASES
Ajay Kumar Verma, Philip Brisk, Paolo Ienne
2006 A conf
Combining algorithm exploration with instruction set design: a case study in elliptic curve cryptography.
DATE
Johann Großschädl, Paolo Ienne, Laura Pozzi, Stefan Tillich, Ajay Kumar Verma
2006 A* conf
Towards the automatic exploration of arithmetic-circuit architectures.
DAC
Ajay Kumar Verma, Paolo Ienne
2004 — conf
Arithmetic Transformations to Maximise the Use of Compressor Trees.
DELTA
Paolo Ienne, Ajay Kumar Verma
2004 A conf
Improved use of the carry-save representation for the synthesis of complex arithmetic circuits.
ICCAD
Ajay Kumar Verma, Paolo Ienne