Ajai Jain

14 papers Misc 3Journal 8Unranked 3
YearRankTypeTitle / Venue / Authors
2024 J jnl
Effect of pin shapes on temperature distribution in friction stir lap joint of AA6061 with AZ31 using numerical simulation.
Int. J. Simul. Process. Model.
Amit Yadav, Ajai Jain, Rajiv Verma
2022 J jnl
An approach for optimisation of flexible flow shop group scheduling with sequence dependent set-up time and preventive maintenance.
Int. J. Comput. Aided Eng. Technol.
Ajai Jain, Avichal Jain
2020 J jnl
An integrated approach for multi-period manufacturing planning of job-shops.
Int. J. Manuf. Res.
Viraj Tyagi, Ajai Jain, P. K. Jain
2016 J jnl
New setup-oriented dispatching rules for a stochastic dynamic job shop manufacturing system with sequence-dependent setup times.
Concurr. Eng. Res. Appl.
Pankaj Sharma, Ajai Jain
2013 J jnl
An approach for integration of process planning and scheduling.
Int. J. Comput. Integr. Manuf.
Rakesh Kumar Phanden, Ajai Jain, Rajiv Verma
2012 J jnl
Experimental Investigation of Machining Characteristics for the WEDM of Al/ZrO2(p)-PRMMC.
Int. J. Manuf. Mater. Mech. Eng.
Sanjeev Kumar Garg, Alakesh Manna, Ajai Jain
2011 — conf
English to Sanskrit machine translation.
ICWET
P. Bahadur, Ajai Jain, D. S. Chauhan
2011 J jnl
Integration of process planning and scheduling: a state-of-the-art review.
Int. J. Comput. Integr. Manuf.
Rakesh Kumar Phanden, Ajai Jain, Rajiv Verma
2003 — conf
Stochastic Image Compression Using Fractals.
ITCC
Aditya Kapoor, Kush Arora, Ajai Jain, G. P. Kapoor
1998 Misc conf
Automatic Test Pattern Generation for Sequential Circuits Using Genetic Algorithms.
VLSI Design
V. Rajesh, Ajai Jain
1998 Misc conf
Testability Preserving and Enhancing Transformations for Robust Delay Fault Testabilit.
VLSI Design
Amey Karkare, Manoj Singla, Ajai Jain
1996 Misc conf
An Efficient Test Generation Technique for Sequential Circuits with Repetitive Sub-Circuits.
VLSI Design
Dhruva R. Chakrabarti, Ajai Jain
1995 — conf
An improved hierarchical test generation technique for combinational circuits with repetitive sub-circuits.
Asian Test Symposium
Dhruva R. Chakrabarti, Ajai Jain
1991 J jnl
A fault-tolerant array processor designed for testability and self-reconfiguration.
IEEE J. Solid State Circuits
Ajai Jain, Babu Mandava, Janusz Rajski, Nicholas C. Rumin