Aitzol Zuloaga

37 papers B 2C 6Journal 14Unranked 15

Year	Rank	Type	Title / Venue / Authors
2025	—	`conf`	A Proof-Of-Concept ASIC RISC-V Based SoC for Industrial Applications. DCIS Sara Alonso, Alejandro Arteaga, Leire Muguira, Carlos Cuadrado, Aitzol Zuloaga, Jaime Jiménez, Jesús Lázaro, Jose Ignacio Garate, José Ángel Araujo, Victor Martínez, Unai Bidarte, Armando Astarloa
2024	J	`jnl`	AXI Lite Redundant On-Chip Bus Interconnect for High Reliability Systems. IEEE Trans. Reliab. Jesús Lázaro, Armando Astarloa, Aitzol Zuloaga, José Ángel Araujo, Jaime Jiménez
2022	—	`conf`	Data content scrubbing approach for SRAM based FPGA designs. ISIE Julen Gomez-Cornejo, Igor Villalta, Itxaso Aranzabal, Iraide Lopez, Aitzol Zuloaga
2017	J	`jnl`	A novel BRAM content accessing and processing method based on FPGA configuration bitstream. Microprocess. Microsystems Julen Gomez-Cornejo, Aitzol Zuloaga, Igor Villalta, Javier Del Ser, Uli Kretzschmar, Jesús Lázaro
2016	C	`conf`	Intelligent gateway for Industry 4.0-compliant production. IECON Armando Astarloa, Unai Bidarte, Jaime Jimenez, Aitzol Zuloaga, Jesús Lázaro
2015	J	`jnl`	PRP and HSR for High Availability Networks in Power Utility Automation: A Method for Redundant Frames Discarding. IEEE Trans. Smart Grid José Ángel Araujo, Jesús Lázaro, Armando Astarloa, Aitzol Zuloaga, Jose Ignacio Garate
2014	—	`conf`	Cost-effective redundancy for ethernet train communications using HSR. ISIE Aitzol Zuloaga, Armando Astarloa, Jaime Jimenez, Jesús Lázaro, Jose Angel Araujo
2013	C	`conf`	Duplicate and circulating frames discard methods for PRP and HSR (IEC62439-3). IECON José Ángel Araujo, Jesús Lázaro, Armando Astarloa, Aitzol Zuloaga, Naiara Moreira
2013	C	`conf`	Fast context reloading lockstep approach for SEUs mitigation in a FPGA soft core processor. IECON Julen Gomez-Cornejo, Aitzol Zuloaga, Uli Kretzschmar, Unai Bidarte, Jaime Jimenez
2013	C	`conf`	PRP and HSR version 1 (IEC 62439-3 Ed.2), improvements and a prototype implementation. IECON José Ángel Araujo, Jesús Lázaro, Armando Astarloa, Aitzol Zuloaga, Alain García
2013	C	`conf`	System-on-Chip implementation of Reliable Ethernet Networks nodes. IECON Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, Mikel Idirin
2012	—	`conf`	High availability automation networks: PRP and HSR ring implementations. ISIE Jose Angel Araujo, Jesús Lázaro, Armando Astarloa, Aitzol Zuloaga, Alain García
2011	—	`conf`	An automatic experimental set-up for robustness analysis of designs implemented on SRAM FPGAS. SoC Uli Kretzschmar, Armando Astarloa, Jesús Lázaro, Jaime Jimenez, Aitzol Zuloaga
2011	J	`jnl`	I2CSec: A secure serial Chip-to-Chip communication protocol. J. Syst. Archit. Jesús Lázaro, Armando Astarloa, Aitzol Zuloaga, Unai Bidarte, Jaime Jimenez
2011	—	`conf`	NoCmodel: An extensible framework for Network-on-Chips modeling. ReCoSoC Oscar Daniel Diaz, Armando Astarloa, Aitzol Zuloaga, Jesús Lázaro, Jaime Jimenez
2010	—	`conf`	An Autonomous Fault Tolerant System for CAN Communications. IEA/AIE (3) Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, José Luis Martín
2009	—	`conf`	AES-Galois Counter Mode Encryption/Decryption FPGA Core for Industrial and Residential Gigabit Ethernet Communications. ARC Jesús Lázaro, Armando Astarloa, Unai Bidarte, Jaime Jimenez, Aitzol Zuloaga
2009	—	`conf`	DNAX-BCU: An Un-clonable Cost-conscious SoPC Implementation for Bus Coupling Units of the European Installation Bus. ICDCS Workshops Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, Jaime Jimenez
2009	—	`conf`	PCIREX: A Fast Prototyping Platform for TMR Dynamically Reconfigurable Systems. ReConFig Armando Astarloa, Jesús Lázaro, Unai Bidarte, Aitzol Zuloaga, Jaime Jimenez
2008	C	`conf`	A Novel Technique for Low Latency Data Gathering in Wireless Sensor Networks. DSD Itziar Marín, Aitzol Zuloaga, Iker Losada
2008	J	`jnl`	LL-MAC: A low latency MAC protocol for wireless self-organised networks. Microprocess. Microsystems Itziar Marín, Jagoba Arias, E. Arceredillo, Aitzol Zuloaga, Iker Losada, Jon Mabe
2007	J	`jnl`	Design of a Master Device for the Multifunction Vehicle Bus. IEEE Trans. Veh. Technol. Jaime Jimenez, José Luis Martín, Unai Bidarte, Armando Astarloa, Aitzol Zuloaga
2007	J	`jnl`	GPS-less location algorithm for wireless sensor networks. Comput. Commun. Jagoba Arias, Jesús Lázaro, Aitzol Zuloaga, Jaime Jimenez, Armando Astarloa
2007	J	`jnl`	Hardware architecture for a general regression neural network coprocessor. Neurocomputing Jesús Lázaro, Jagoba Arias, Armando Astarloa, Unai Bidarte, Aitzol Zuloaga
2007	J	`jnl`	Tornado: A self-reconfiguration control system for core-based multiprocessor CSoPCs. J. Syst. Archit. Armando Astarloa, Aitzol Zuloaga, Unai Bidarte, José Luis Martín, Jesús Lázaro, Jaime Jimenez
2006	J	`jnl`	Comparison of two designs for the multifunction vehicle bus. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jaime Jimenez, José Luis Martín, Aitzol Zuloaga, Unai Bidarte, Jagoba Arias
2006	—	`conf`	Node Synchronization in Wireless Sensor Networks. ICWMC Jagoba Arias, Eduardo Santos, Itziar Marín, Jaime Jimenez, Jesús Lázaro, Aitzol Zuloaga
2006	J	`jnl`	SOM Segmentation of gray scale images for optical recognition. Pattern Recognit. Lett. Jesús Lázaro, Jagoba Arias, José Luis Martín, Aitzol Zuloaga, Carlos Cuadrado
2005	J	`jnl`	Hardware implementation of optical flow constraint equation using FPGAs. Comput. Vis. Image Underst. José L. Martín-Sánchez, Aitzol Zuloaga, Carlos Cuadrado, Jesús Lázaro, Unai Bidarte
2005	J	`jnl`	Multiprocessor SoPC-Core for FAT volume computation. Microprocess. Microsystems Armando Astarloa, Unai Bidarte, Jesús Lázaro, Aitzol Zuloaga, Jagoba Arias
2004	B	`conf`	A Self-Reconfiguration Framework for Multiprocessor CSoPCs. FPL Armando Astarloa, Jesús Lázaro, Unai Bidarte, José Luis Martín, Aitzol Zuloaga
2004	—	`conf`	Co-simulation Virtual Platform for Reconfigurable Multiprocessor Hybrid Cores Development. MSV/AMCS Armando Astarloa, Jesús Lázaro, Jagoba Arias, Unai Bidarte, Aitzol Zuloaga
2004	—	`conf`	Doppler Location Algorithm for Wireless Sensor Networks. International Conference on Wireless Networks Jagoba Arias, Jesús Lázaro, Aitzol Zuloaga, Jaime Jimenez
2004	J	`jnl`	Malguki: an RSSI based ad hoc location algorithm. Microprocess. Microsystems Jagoba Arias, Aitzol Zuloaga, Jesús Lázaro, Jon Andreu, Armando Astarloa
2003	B	`conf`	Core-Based Reusable Architecture for Slave Circuits with Extensive Data Exchange Requirements. FPL Unai Bidarte, Armando Astarloa, Aitzol Zuloaga, Jaime Jimenez, Iñigo Martínez de Alegría
2001	—	`conf`	Software Workbench for Movement Estimation based on Optical Flow Computation. VIIP José Luis Martín, Aitzol Zuloaga, Josu Cruzado
1998	—	`conf`	Hardware Architecture for Optical Flow Estimation in Real Time. ICIP (3) Aitzol Zuloaga, José Luis Martín, Joseba Ezquerra