Aiqun Cao

12 papers A* 1A 1C 1Journal 3Unranked 6
YearRankTypeTitle / Venue / Authors
2022 — conf
Triple-play of Hyperconvergency, Analytics, and AI Innovations in the SysMoore Era.
ISPD
Aiqun Cao
2012 — conf
Clock mesh framework.
ISQED
Pinaki Chakrabarti, Vikram Bhatt, Dwight D. Hill, Aiqun Cao
2007 J jnl
SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips.
IEEE Trans. Very Large Scale Integr. Syst.
Ruibing Lu, Aiqun Cao, Cheng-Kok Koh
2006 J jnl
Postlayout optimization for synthesis of Domino circuits.
ACM Trans. Design Autom. Electr. Syst.
Aiqun Cao, Ruibing Lu, Chen Li, Cheng-Kok Koh
2005 — conf
Improving the scalability of SAMBA bus architecture.
ASP-DAC
Ruibing Lu, Aiqun Cao, Cheng-Kok Koh
2005 — conf
Post-layout logic duplication for synthesis of domino circuits with complex gates.
ASP-DAC
Aiqun Cao, Ruibing Lu, Cheng-Kok Koh
2005 J jnl
Synthesis of skewed logic circuits.
ACM Trans. Design Autom. Electr. Syst.
Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy
2004 A* conf
Post-layout logic optimization of domino circuits.
DAC
Aiqun Cao, Cheng-Kok Koh
2003 — conf
Integer linear programming-based synthesis of skewed logic circuits.
ASP-DAC
Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy
2003 C conf
Non-Crossing OBDDs for Mapping to Regular Circuit Structures.
ICCD
Aiqun Cao, Cheng-Kok Koh
2002 — conf
Synthesis of Selectively Clocked Skewed Logic Circuits.
ISQED
Aiqun Cao, Naran Sirisantana, Cheng-Kok Koh, Kaushik Roy
2001 A conf
Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications.
ISLPED
Naran Sirisantana, Aiqun Cao, Shawn Davidson, Cheng-Kok Koh, Kaushik Roy