Aiman H. El-Maleh

51 papers A* 2C 3Misc 1Journal 32Unranked 13
YearRankTypeTitle / Venue / Authors
2026 J jnl
HQC
IEEE Open J. Commun. Soc.
Laiba Tanveer, Zeeshan Kaleem, Aiman H. El-Maleh, Muhammad Afaq, Abdulaziz Barnawi, Huseyin Arslan
2025 J jnl
C3Net: Context-Contrast Network for Camouflaged Object Detection.
CoRR
Baber Jan, Aiman H. El-Maleh, Abdul Jabbar Siddiqui, Abdul Bais, Saeed Anwar
2025 J jnl
Multiple-Input Floating-Point Adders: A Comprehensive Review.
IEEE Access
Sami Ul Haq, Aiman H. El-Maleh, Ali Alsuwaiyan
2025 J jnl
SPEGNet: Synergistic Perception-Guided Network for Camouflaged Object Detection.
CoRR
Baber Jan, Saeed Anwar, Aiman H. El-Maleh, Abdul Jabbar Siddiqui, Abdul Bais
2022 J jnl
DE-ZFP: An FPGA implementation of a modified ZFP compression/decompression algorithm.
Microprocess. Microsystems
Mahmoud Habboush, Aiman H. El-Maleh, Muhammad E. S. Elrabaa, Saleh Alsaleh
2021 J jnl
Time redundancy and gate sizing soft error-tolerant based adder design.
Integr.
Aiman H. El-Maleh, Ghashmi H. Bin Talib
2018 J jnl
Double Modular Redundancy (DMR) Based Fault Tolerance Technique for Combinational Circuits.
J. Circuits Syst. Comput.
Ahmad T. Sheikh, Aiman H. El-Maleh
2017 J jnl
A Fault Tolerance Technique for Combinational Circuits Based on Selective-Transistor Redundancy.
IEEE Trans. Very Large Scale Integr. Syst.
Ahmad T. Sheikh, Aiman H. El-Maleh, Muhammad E. S. Elrabaa, Sadiq M. Sait
2017 J jnl
A probabilistic pairwise swap search state assignment algorithm for sequential circuit optimization.
Integr.
Aiman H. El-Maleh
2017 J jnl
An integrated fault tolerance technique for combinational circuits based on implications and transistor sizing.
Integr.
Ahmad T. Sheikh, Aiman H. El-Maleh
2017 J jnl
Finite state machine-based fault tolerance technique with enhanced area and power of synthesised sequential circuits.
IET Comput. Digit. Tech.
Aiman H. El-Maleh
2016 J jnl
Cuckoo search based resource optimization of datacenters.
Appl. Intell.
Sadiq M. Sait, Abubakar Bala, Aiman H. El-Maleh
2016 J jnl
Majority-based evolution state assignment algorithm for area and power optimisation of sequential circuits.
IET Comput. Digit. Tech.
Aiman H. El-Maleh
2015 — conf
A sequential circuit fault tolerance technique with enhanced area and power.
ISSPIT
Aiman H. El-Maleh
2015 J jnl
Simulation-Based Method for Synthesizing Soft Error Tolerant Combinational Circuits.
IEEE Trans. Reliab.
Aiman H. El-Maleh, Khaled A. Daud
2015 J jnl
State assignment for area minimization of sequential circuits based on cuckoo search optimization.
Comput. Electr. Eng.
Aiman H. El-Maleh, Sadiq M. Sait, Abubakar Bala
2015 — conf
State assignment for power optimization of sequential circuits based on a probabilistic pairwise swap search algorithm.
ISSPIT
Aiman H. El-Maleh
2015 J jnl
Towards a Test Definition Language for Integrated Circuits.
J. Circuits Syst. Comput.
Mohammad R. Alshayeb, Muhammad E. S. Elrabaa, Ayman Hroub, Amran Al-Aghbari, Aiman H. El-Maleh, Abdelhafid Bouhraoua
2014 J jnl
A finite state machine based fault tolerance technique for sequential circuits.
Microelectron. Reliab.
Aiman H. El-Maleh, Ayed S. Al-Qahtani
2014 J jnl
A generalized modular redundancy scheme for enhancing fault tolerance of combinational circuits.
Microelectron. Reliab.
Aiman H. El-Maleh, Feras Chikh Oughali
2013 J jnl
Binary particle swarm optimization (BPSO) based state assignment for area minimization of sequential circuits.
Appl. Soft Comput.
Aiman H. El-Maleh, Ahmad T. Sheikh, Sadiq M. Sait
2013 — conf
Enhancing Reliability of Combinational Circuits against Soft Errors by Using a Generalized Modular Redundancy Scheme.
ISED
Aiman H. El-Maleh, Feras Chikh Oughali
2010 J jnl
A scheme of test data compression based on coding of even bits marking and selective output inversion.
Comput. Electr. Eng.
Wenfa Zhan, Huaguo Liang, Cuiyun Jiang, Zhengfeng Huang, Aiman H. El-Maleh
2009 J jnl
Defect-tolerant n
IET Comput. Digit. Tech.
Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Melouki, Farhan Khan
2009 J jnl
Reconfigurable broadcast scan compression using relaxation-based test vector decomposition.
IET Comput. Digit. Tech.
Aiman H. El-Maleh, Mustafa Imran Ali, Ahmad A. Al-Yamani
2008 J jnl
Efficient test compression technique based on block merging.
IET Comput. Digit. Tech.
Aiman H. El-Maleh
2008 J jnl
Test data compression for system-on-a-chip using extended frequency-directed run-length code.
IET Comput. Digit. Tech.
Aiman H. El-Maleh
2008 C conf
Transistor-level based defect tolerance for reliable nanoelectronics.
AICCSA
Aiman H. El-Maleh, Bashir M. Al-Hashimi, Aissa Melouki
2007 — conf
A Reconfigurable Broadcast Scan Compression Scheme Using Relaxation Based Test Vector Decompos.
ATS
Aiman H. El-Maleh, Mustafa Imran Ali, Ahmad A. Al-Yamani
2006 J jnl
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse-Order Restoration and Test Relaxation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Aiman H. El-Maleh, S. Saqib Khursheed, Sadiq M. Sait
2006 J jnl
Evolutionary algorithms for VLSI multi-objective netlist partitioning.
Eng. Appl. Artif. Intell.
Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Abaji
2006 C conf
Finite state machine state assignment for area and power minimization.
ISCAS
Aiman H. El-Maleh, Sadiq M. Sait, F. Nawaz Khan
2005 — conf
Efficient Static Compaction Techniques for Sequential Circuits Based on Reverse Order Restoration and Test Relaxation.
Asian Test Symposium
Aiman H. El-Maleh, S. Saqib Khursheed, Sadiq M. Sait
2004 J jnl
An efficient test relaxation technique for synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Aiman H. El-Maleh, Khaled Al-Utaibi
2003 — conf
A hybrid test compression technique for efficient testing of systems-on-a-chip.
ICECS
Aiman H. El-Maleh
2003 — conf
A static test compaction technique for combinational circuits based on independent fault clustering.
ICECS
Yahya E. Osais, Aiman H. El-Maleh
2003 Misc conf
An Efficient Test Relaxation Technique for Synchronous Sequential Circuits.
VTS
Aiman H. El-Maleh, Khaled Al-Utaibi
2003 — conf
Enhancing performance of iterative heuristics for VLSI netlist partitioning.
ICECS
Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Abaji
2003 — conf
General iterative heuristics for VLSI multiobjective partitioning.
ISCAS (5)
Sadiq M. Sait, Aiman H. El-Maleh, Raslan H. Al-Abaji
2003 — conf
On efficient extraction of partially specified test sets for synchronous sequential circuits.
ISCAS (5)
Aiman H. El-Maleh, Khaled Al-Utaibi
2003 — conf
Simulated evolution algorithm for multiobjective VLSI netlist bi-partitioning.
ISCAS (5)
Sadiq M. Sait, Aiman H. El-Maleh, Rush H. Al-Abuji
2003 J jnl
Test vector decomposition-based static compaction algorithms for combinational circuits.
ACM Trans. Design Autom. Electr. Syst.
Aiman H. El-Maleh, Yahya E. Osais
2002 — conf
Extended frequency-directed run-length code with improved application to system-on-a-chip test data compression.
ICECS
Aiman H. El-Maleh, Raslan H. Al-Abaji
2001 — conf
A retiming-based test pattern generator design for built-in self test of data path architectures.
ISCAS (4)
Aiman H. El-Maleh, Yahya E. Osais
2001 C conf
Fuzzified Iterative Algorithms for Performance Driven Low Power VLSI Placement.
ICCD
Sadiq M. Sait, Habib Youssef, Junaid A. Khan, Aiman H. El-Maleh
1998 A* conf
A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance.
DAC
Aiman H. El-Maleh, Mark Kassab, Janusz Rajski
1997 J jnl
Behavior and testability preservation under the retiming transformation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly
1996 J jnl
A complexity analysis of sequential ATPG.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Thomas E. Marchok, Aiman H. El-Maleh, Wojciech Maly, Janusz Rajski
1995 J jnl
Delay-fault testability preservation of the concurrent decomposition and factorization transformations.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Aiman H. El-Maleh, Janusz Rajski
1995 A* conf
On Test Set Preservation of Retimed Circuits.
DAC
Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly
1995 J jnl
Testability Implications of Performance-Driven Logic Synthesis.
IEEE Des. Test Comput.
Thomas E. Marchok, Aiman H. El-Maleh, Janusz Rajski, Wojciech Maly