| Year | Rank | Type | Title / Venue / Authors |
|---|---|---|---|
| 2025 | J | jnl |
IEEE Trans. Artif. Intell.
|
| 2025 | A* | conf |
CVPR
|
| 2025 | J | jnl |
CoRR
|
| 2025 | J | jnl |
CoRR
|
| 2025 | A* | conf |
ICML
|
| 2025 | J | jnl |
CoRR
|
| 2025 | J | jnl |
IEEE Trans. Artif. Intell.
|
| 2025 | J | jnl |
Neuromorph. Comput. Eng.
|
| 2024 | A* | conf |
NeurIPS
|
| 2024 | J | jnl |
CoRR
|
| 2024 | J | jnl |
CoRR
|
| 2024 | J | jnl |
CoRR
|
| 2024 | J | jnl |
CoRR
|
| 2023 | — | conf |
ICSCC
|
| 2023 | — | conf |
ICCAI
|
| 2023 | — | conf |
RICAI
|
| 2023 | J | jnl |
CoRR
|
| 2022 | J | jnl |
CoRR
|
| 2022 | J | jnl |
CoRR
|
| 2021 | J | jnl |
IEEE Trans. Circuits Syst. I Regul. Pap.
|
| 2020 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2019 | — | conf |
CICC
|
| 2019 | J | jnl |
IEEE Trans. Very Large Scale Integr. Syst.
|
| 2018 | J | jnl |
Integr.
|
| 2018 | C | conf |
Pin-Efficient 12-Bit 8-Wire 8-Level Permutation Coding for High-Speed Parallel Wireline Tranceivers.
ISCAS
|
| 2017 | J | jnl |
IEEE Trans. Circuits Syst. I Regul. Pap.
|
| 2016 | C | conf |
ISCAS
|
| 2016 | C | conf |
ISCAS
|