Aijiao Cui

58 papers C 14Misc 2Journal 14Unranked 27
YearRankTypeTitle / Venue / Authors
2025 J jnl
Acceleration of the Bootstrapping in TFHE by FPGA.
IEEE Trans. Emerg. Top. Comput.
Jian Zhang, Aijiao Cui, Yier Jin
2025 — conf
Bug Hunting in the RISC-V SoC: The 1
AsianHOST
Lei Peng, Jiacheng Zhu, Qizhi Zhang, Shibo Tang, Xingxin Wang, Xinyu Zheng, Yaxuan Zhao, Aijiao Cui, Wei Hu, Jiaji He, Peng Fei Qiu
2024 — conf
A Hardware Security Evaluation Platform on RISC-V SoC.
ITC-Asia
Xiaolong Cheng, Aijiao Cui, Yier Jin
2024 J jnl
Non-Invasive Reverse Engineering of One-Hot Finite State Machines Using Scan Dump Data.
IEEE Trans. Emerg. Top. Comput.
Zhaoxuan Dong, Aijiao Cui, Hao Lu
2024 — conf
SecRiSBen: A RISC-V based SoC Benchmark for Evaluation of Security Verification Tools.
AsianHOST
Maoyuan Cai, Aijiao Cui, Yier Jin
2023 — conf
A Lightweight Authentication Scheme with PE-Based Unclonable Label.
AsianHOST
Renchao Li, Zhen Weng, Aijiao Cui, Gang Qu
2023 — conf
A Low-overhead PUF-based Secure Scan Design.
ISQED
Wei Zhou, Aijiao Cui, Cassi Chen, Gang Qu
2022 — conf
A Memristor-based Secure Scan Design against the Scan-based Side-Channel Attacks.
ACM Great Lakes Symposium on VLSI
Mengqiang Lu, Aijiao Cui, Yan Shao, Gang Qu
2022 — conf
Building Hardware Security Primitives Using Scan-based Design-for-Testability.
MWSCAS
Omid Aramoon, Gang Qu, Aijiao Cui
2022 J jnl
SATAM: A SAT Attack Resistant Active Metering Against IC Overbuilding.
IEEE Trans. Emerg. Top. Comput.
Aijiao Cui, Zhen Weng, Hui Zhang, Gang Qu, Huawei Li
2021 J jnl
A New PUF Based Lock and Key Solution for Secure In-Field Testing of Cryptographic Chips.
IEEE Trans. Emerg. Top. Comput.
Aijiao Cui, Chip-Hong Chang, Wei Zhou, Yue Zheng
2021 — conf
Identification of Counter Registers through Full Scan Chain.
ITC-Asia
Qidong Wang, Aijiao Cui, Gang Qu
2021 J jnl
Identification of FSM State Registers by Analytics of Scan-Dump Data.
IEEE Trans. Inf. Forensics Secur.
Aijiao Cui, Chengkang He, Chip-Hong Chang, Hao Lu
2021 — conf
Novel Memristor-based Nonvolatile D Latch and Flip-flop Designs.
ISQED
Zhenxing Chang, Aijiao Cui, Ziming Wang, Gang Qu
2020 J jnl
A Guaranteed Secure Scan Design Based on Test Data Obfuscation by Cryptographic Hash.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Aijiao Cui, Mengyang Li, Gang Qu, Huawei Li
2020 — conf
A Low-Cost Fault Injection Attack Resilient FSM Design.
SoCC
Ziming Wang, Aijiao Cui, Gang Qu
2020 — conf
A New Aging Sensor for the Detection of Recycled ICs.
ACM Great Lakes Symposium on VLSI
Zhichao Xu, Aijiao Cui, Gang Qu
2020 Misc conf
A New Secure Scan Design with PUF-based Key for Authentication.
VTS
Qidong Wang, Aijiao Cui, Gang Qu, Huawei Li
2020 — conf
How to Retrieve PUF Response from a Fabricated Chip Securely?
ISQED
Aijiao Cui, Yuxi Wang
2019 — conf
A Memristor-based Scan Hold Flip-Flop.
NVMSA
Aijiao Cui, Zhenxing Chang, Ziming Wang, Gang Qu, Huawei Li
2019 C conf
A New Pay-Per-Use Scheme for the Protection of FPGA IP.
ISCAS
Peiqi Sun, Aijiao Cui
2019 Misc conf
A Secure and Low-overhead Active IC Metering Scheme.
VTS
Aijiao Cui, Yan Yang, Gang Qu, Huawei Li
2019 — conf
Identification of State Registers of FSM Through Full Scan by Data Analytics.
AsianHOST
Chengkang He, Aijiao Cui, Chip-Hong Chang
2018 — conf
A New Scheme to Extract PUF Information by Scan Chain.
ATS
Aijiao Cui, Wei Zhou, Gang Qu, Huawei Li
2018 — conf
A low-overhead PUF based on parallel scan design.
ASP-DAC
Wenxuan Wang, Aijiao Cui, Gang Qu, Huawei Li
2018 — conf
Balancing Testability and Security by Configurable Partial Scan Design.
ITC-Asia
Xi Chen, Omid Aramoon, Gang Qu, Aijiao Cui
2018 — conf
Partial Scan Design Against Scan-Based Side Channel Attacks.
TrustCom/BigDataSE
Xi Chen, Zhaojun Lu, Gang Qu, Aijiao Cui
2017 — conf
A New Active IC Metering Technique Based on Locking Scan Cells.
ATS
Aijiao Cui, Xuesen Qian, Gang Qu, Huawei Li
2017 C conf
A new watermarking scheme on scan chain ordering for hard IP protection.
ISCAS
Xiaonan Huang, Aijiao Cui, Chip-Hong Chang
2017 — conf
How to Secure Scan Design Against Scan-Based Side-Channel Attacks?
ATS
Wei Zhou, Aijiao Cui, Huawei Li, Gang Qu
2017 C conf
Practical IP watermarking and fingerprinting methods for ASIC designs.
ISCAS
Xi Chen, Gang Qu, Aijiao Cui
2017 — conf
Scan chain based IP fingerprint and identification.
ISQED
Xi Chen, Gang Qu, Aijiao Cui, Carson Dunbar
2017 J jnl
Static and Dynamic Obfuscations of Scan Data Against Scan-Based Side-Channel Attacks.
IEEE Trans. Inf. Forensics Secur.
Aijiao Cui, Yanhui Luo, Chip-Hong Chang
2017 J jnl
Why current secure scan designs fail and how to fix them?
Integr.
Aijiao Cui, Yanhui Luo, Huawei Li, Gang Qu
2016 C conf
A new countermeasure against scan-based side-channel attacks.
ISCAS
Yanhui Luo, Aijiao Cui, Gang Qu, Huawei Li
2016 C conf
An improved test power optimization method by insertion of linear functions.
ISCAS
Lucheng He, Aijiao Cui, Mengyang Li, André Ivanov
2016 — conf
An ultra-low overhead LUT-based PUF for FPGA.
AsianHOST
Jiadong Wang, Aijiao Cui, Mengyang Li, Gang Qu, Huawei Li
2016 — ch.
Digital Fingerprint: A Practical Hardware Security Primitive.
Digital Fingerprinting
Gang Qu, Carson Dunbar, Xi Chen, Aijiao Cui
2015 C conf
A new decompressor with ordered parallel scan design for reduction of test data and test time.
ISCAS
Tingting Yu, Aijiao Cui, Mengyang Li, André Ivanov
2015 C conf
An improved scan design for minimization of test power under routing constraint.
ISCAS
Aijiao Cui, Tingting Yu, Gang Qu, Mengyang Li
2015 J jnl
Design of Optimal Scan Tree Based on Compact Test Patterns for Test Time Reduction.
IEEE Trans. Computers
Linfeng Chen, Aijiao Cui, Chip-Hong Chang
2015 — conf
Reliable and Anti-cloning PUFs Based on Configurable Ring Oscillators.
CAD/Graphics
Mingze Gao, Khai Lai, Jiliang Zhang, Gang Qu, Aijiao Cui, Qiang Zhou
2015 J jnl
Ultra-Low Overhead Dynamic Watermarking on Scan Design for Hard IP Protection.
IEEE Trans. Inf. Forensics Secur.
Aijiao Cui, Gang Qu, Yan Zhang
2014 C conf
A low-overhead dynamic watermarking scheme on scan design for easy authentication.
ISCAS
Aijiao Cui, Wei Liang, Gang Qu
2014 J jnl
A refined affine approximation method of multiplication for range analysis in word-length optimization.
EURASIP J. Adv. Signal Process.
Ruiyi Sun, Yan Zhang, Aijiao Cui
2014 — conf
An improved scan cell ordering method using the scan cells with complementary outputs.
ISIC
Mengyang Li, Aijiao Cui, Tingting Yu
2013 C conf
A power-efficient scan tree design by exploring the Q'-D connection.
ISCAS
Linfeng Chen, Aijiao Cui
2013 — conf
An Efficient Zero-Aliasing Space Compactor Based on Elementary Gates Combined with XOR Gates.
CAD/Graphics
Yongxia Liu, Aijiao Cui
2012 — conf
A post-processing scan-chain watermarking scheme for VLSI intellectual property protection.
APCCAS
Aijiao Cui, Chip-Hong Chang
2011 J jnl
A Robust FSM Watermarking Scheme for IP Protection of Sequential Circuit Design.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Aijiao Cui, Chip-Hong Chang, Sofiène Tahar, Amr Talaat Abdel-Hamid
2011 C conf
A hybrid watermarking scheme for sequential functions.
ISCAS
Aijiao Cui, Chip-Hong Chang, Li Zhang
2010 J jnl
Synthesis-for-Testability Watermarking for Field Authentication of VLSI Intellectual Property.
IEEE Trans. Circuits Syst. I Regul. Pap.
Chip-Hong Chang, Aijiao Cui
2009 C conf
An Improved Publicly Detectable Watermarking Scheme based on Scan Chain Ordering.
ISCAS
Aijiao Cui, Chip-Hong Chang
2008 J jnl
IP Watermarking Using Incremental Technology Mapping at Logic Synthesis Level.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Aijiao Cui, Chip-Hong Chang, Sofiène Tahar
2008 C conf
Intellectual property authentication by watermarking scan chain in design-for-testability flow.
ISCAS
Aijiao Cui, Chip-Hong Chang
2007 C conf
Watermarking for IP Protection through Template Substitution at Logic Synthesis Level.
ISCAS
Aijiao Cui, Chip-Hong Chang
2006 — conf
Kernel Extraction for Watermarking Combinational Logic Networks.
APCCAS
Aijiao Cui, Chip-Hong Chang
2006 C conf
Stego-signature at logic synthesis level for digital design IP protection.
ISCAS
Aijiao Cui, Chip-Hong Chang