Ai He

11 papers C 2Journal 5Unranked 4
YearRankTypeTitle / Venue / Authors
2026 J jnl
Remaining useful life prediction of aero-engine using pyramid temporal convolutional network with fused complementary attention.
Reliab. Eng. Syst. Saf.
Kun Wang, Ai He, Jiashuai Liu, Qifan Zhou, Zhongzhi Hu, Jinshen Wang
2024 J jnl
A two-stage slicer employing body biasing for 64-Gb/s PAM4 wireline receiver in 22-nm FDSOI technology.
Microelectron. J.
Ai He, Binhong Li, Jianzhong Li, Xing Zhao, Jincai Guo, Jianping Wang, Xiangqian Zeng, Yun Wang, Tianchun Ye, Quan Xue
2023 J jnl
Shrinking Factor Dimension: A Reduced-Rank Approach.
Manag. Sci.
Ai He, Dashan Huang, Jiaen Li, Guofu Zhou
2021 J jnl
56 Gb/s PAM4 receiver with an overshoot compensation scheme in 28 nm CMOS technology.
Microelectron. J.
Ai He, Weixin Gai, Bingyi Ye, Boyang Zhang, Kai Sheng, Yuanliang Li
2021 — conf
An Adaptive DFE Using Pattern-Dependent Data-Level Reference in 28 nm CMOS Technology.
ASICON
Ai He, Weixin Gai, Kai Sheng, Ninghuang Li
2021 J jnl
Equal-slope baud-rate CDR algorithm with optimized eye opening.
Microelectron. J.
Xiao Xiang, Weixin Gai, Ai He, Hang Zhou, Dong Yanchi
2019 C conf
An 8-12GHz 0.92° Phase Error Quadrature Clock Generator Based on Two-Stage Poly Phase Filter with Intermediate Point Compensation.
ISCAS
Xiao Xiang, Weixin Gai, Linqi Shi, Ai He, Kai Sheng
2019 C conf
Double-Comparison Settling Error Correction Scheme for Binary Scaled SAR ADCs.
ISCAS
Ai He, Weixin Gai, Yufan Feng, Zhongzhu Pu, Xiao Xiang
2018 — conf
A 32Gb/s 133mW PAM-4 transceiver with DFE based on adaptive clock phase and threshold voltage in 65nm CMOS.
ISSCC
Liangxiao Tang, Weixin Gai, Linqi Shi, Xiao Xiang, Kai Sheng, Ai He
2015 — conf
Two-Way Graphic Password for Mobile User Authentication.
CSCloud
Ming Jiang, Ai He, Kuangyu Wang, Zhengyi Le
2013 — conf
Reconstructing Big Semantic Similarity Networks.
TextGraphs@EMNLP
Ai He, Shefali Sharma, Chun-Nan Hsu