Ahmed Louri - RankMe

141 papers A* 26A 14B 2C 5Journal 59Unranked 35

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	EpGAT: integrating epigenetics and 3D genome structure to predict alternative splicing and polyadenylation. Briefings Bioinform. Sudipto Baul, Naima Ahmed Fahmi, Guangyu Wang, Hao Zheng, Ahmed Louri, Jeongsik Yong, Wei Zhang
2025	A	`conf`	A High-Performance and Flexible Accelerator for Dynamic Graph Convolutional Networks. DATE Yingnan Zhao, Ke Wang, Ahmed Louri
2025	—	`conf`	Algorithmic Strategies for Sustainable Reuse of Neural Network Accelerators with Permanent Faults. DFT Youssef A. Ait Alama, Sampada Sakpal, Ke Wang, Razvan C. Bunescu, Avinash Karanth, Ahmed Louri
2025	A*	`conf`	DiTile-DGNN: An Efficient Accelerator for Distributed Dynamic Graph Neural Network Inference. ISCA Jiaqi Yang, Hao Zheng, Ahmed Louri
2025	J	`jnl`	Extending Energy-Efficient and Scalable DNN Training and Inference With 3-D Photonic Accelerator. IEEE J. Emerg. Sel. Topics Circuits Syst. Juliana Curry, Yuan Li, Ahmed Louri, Avinash Karanth, Razvan C. Bunescu
2025	J	`jnl`	FORT-GCN: A Fault-Tolerant and Adaptive Accelerator Design for Efficient Graph Convolutional Network Inference. ACM Trans. Embed. Comput. Syst. Ke Wang, Yingnan Zhao, Ahmed Louri
2025	J	`jnl`	Fault Tolerance in Triplet Network Training: Analysis, Evaluation and Protection Methods. IEEE Trans. Emerg. Top. Comput. Ziheng Wang, Farzad Niknia, Shanshan Liu, Pedro Reviriego, Ahmed Louri, Fabrizio Lombardi
2025	J	`jnl`	HS-GCN: A High-Performance, Sustainable, and Scalable Chiplet-Based Accelerator for Graph Convolutional Network Inference. IEEE Trans. Sustain. Comput. Yingnan Zhao, Ke Wang, Ahmed Louri
2025	A*	`conf`	I-DGNN: A Graph Dissimilarity-based Framework for Designing Scalable and Efficient DGNN Accelerators. HPCA Jiaqi Yang, Hao Zheng, Ahmed Louri
2025	J	`jnl`	MERIT: A Sustainable DNN Accelerator Design With Photonic Phase-Change Memory. IEEE Trans. Sustain. Comput. Yuan Li, Ahmed Louri, Avinash Karanth
2024	J	`jnl`	A Balanced Sparse Matrix Convolution Accelerator for Efficient CNN Training. IEEE Trans. Circuits Syst. I Regul. Pap. Yuechen Chen, Ahmed Louri, Shanshan Liu, Fabrizio Lombardi
2024	J	`jnl`	A High-Performance and Energy-Efficient Photonic Architecture for Multi-DNN Acceleration. IEEE Trans. Parallel Distributed Syst. Yuan Li, Ahmed Louri, Avinash Karanth
2024	J	`jnl`	Algorithmic Strategies for Sustainable Reuse of Neural Network Accelerators with Permanent Faults. CoRR Youssef A. Ait Alama, Sampada Sakpal, Ke Wang, Razvan C. Bunescu, Avinash Karanth, Ahmed Louri
2024	A*	`conf`	An Efficient Hardware Accelerator Design for Dynamic Graph Convolutional Network (DGCN) Inference. DAC Yingnan Zhao, Ke Wang, Jiaqi Yang, Ahmed Louri
2024	A	`conf`	Aurora: A Versatile and Flexible Accelerator for Graph Neural Networks. IPDPS Jiaqi Yang, Hao Zheng, Ahmed Louri
2024	J	`jnl`	Morph-GCNX: A Universal Architecture for High-Performance and Energy-Efficient Graph Convolutional Network Acceleration. IEEE Trans. Sustain. Comput. Ke Wang, Hao Zheng, Jiajun Li, Ahmed Louri
2024	J	`jnl`	OPT-GCN: A Unified and Scalable Chiplet-Based Accelerator for High-Performance and Energy-Efficient GCN Computation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yingnan Zhao, Ke Wang, Ahmed Louri
2024	—	`conf`	PCM Enabled Low-Power Photonic Accelerator for Inference and Training on Edge Devices. IPDPS (Workshops) Juliana Curry, Ahmed Louri, Avinash Karanth, Razvan C. Bunescu
2024	A*	`conf`	VITA: ViT Acceleration for Efficient 3D Human Mesh Recovery via Hardware-Algorithm Co-Design. DAC Shilin Tian, Chase Szafranski, Ce Zheng, Fan Yao, Ahmed Louri, Chen Chen, Hao Zheng
2024	J	`jnl`	Versa-DNN: A Versatile Architecture Enabling High-Performance and Energy-Efficient Multi-DNN Acceleration. IEEE Trans. Parallel Distributed Syst. Jiaqi Yang, Hao Zheng, Ahmed Louri
2023	B	`conf`	A Silicon Photonic Multi-DNN Accelerator. PACT Yuan Li, Ahmed Louri, Avinash Karanth
2023	J	`jnl`	A Technique for Approximate Communication in Network-on-Chips for Image Classification. IEEE Trans. Emerg. Top. Comput. Yuechen Chen, Shanshan Liu, Fabrizio Lombardi, Ahmed Louri
2023	A	`conf`	ARIES: Accelerating Distributed Training in Chiplet-Based Systems via Flexible Interconnects. ICCAD Lingxiang Yin, Amir Ghazizadeh, Ahmed Louri, Hao Zheng
2023	J	`jnl`	Error-Resilient Data Compression With Tunstall Codes. IEEE Trans. Circuits Syst. I Regul. Pap. Shanshan Liu, Pedro Reviriego, Anees Ullah, Ahmed Louri, Fabrizio Lombardi
2023	A*	`conf`	Flumen: Dynamic Processing in the Photonic Interconnect. ISCA Kyle Shiflett, Avinash Karanth, Razvan C. Bunescu, Ahmed Louri
2023	J	`jnl`	GShuttle: Optimizing Memory Access Efficiency for Graph Convolutional Neural Network Accelerators. J. Comput. Sci. Technol. Jiajun Li, Ke Wang, Hao Zheng, Ahmed Louri
2023	C	`conf`	Polyform: A Versatile Architecture for Multi-DNN Execution via Spatial and Temporal Acceleration. ICCD Lingxiang Yin, Amir Ghazizadeh, Shilin Tian, Ahmed Louri, Hao Zheng
2023	J	`jnl`	Slack-Aware Packet Approximation for Energy-Efficient Network-on-Chips. IEEE Trans. Sustain. Comput. Yuechen Chen, Ahmed Louri, Shanshan Liu, Fabrizio Lombardi
2023	A*	`conf`	Venus: A Versatile Deep Neural Network Accelerator Architecture Design for Multiple Applications. DAC Jiaqi Yang, Hao Zheng, Ahmed Louri
2022	J	`jnl`	A Delta Sigma Modulator-Based Stochastic Divider. IEEE Trans. Circuits Syst. I Regul. Pap. Xiaochen Tang, Shanshan Liu, Farzad Niknia, Pedro Reviriego, Ziheng Wang, Wei Tang, Ahmed Louri, Fabrizio Lombardi
2022	A	`conf`	AGAPE: Anomaly Detection with Generative Adversarial Network for Improved Performance, Energy, and Security in Manycore Systems. DATE Ke Wang, Hao Zheng, Yuan Li, Jiajun Li, Ahmed Louri
2022	J	`jnl`	AdaPrune: An Accelerator-Aware Pruning Technique for Sustainable CNN Accelerators. IEEE Trans. Sustain. Comput. Jiajun Li, Ahmed Louri
2022	—	`conf`	Adapt-Flow: A Flexible DNN Accelerator Architecture for Heterogeneous Dataflow Implementation. ACM Great Lakes Symposium on VLSI Jiaqi Yang, Hao Zheng, Ahmed Louri
2022	J	`jnl`	Agile: A Learning-Enabled Power and Performance-Efficient Network-on-Chip Design. IEEE Trans. Emerg. Top. Comput. Hao Zheng, Ahmed Louri
2022	—	`conf`	Approximate Network-on-Chips with Application to Image Classification. NAS Yuechen Chen, Ahmed Louri, Shanshan Liu, Fabrizio Lombardi
2022	J	`jnl`	Ascend: A Scalable and Energy-Efficient Deep Neural Network Accelerator With Photonic Interconnects. IEEE Trans. Circuits Syst. I Regul. Pap. Yuan Li, Ke Wang, Hao Zheng, Ahmed Louri, Avinash Karanth
2022	C	`conf`	FSA: An Efficient Fault-tolerant Systolic Array-based DNN Accelerator Architecture. ICCD Yingnan Zhao, Ke Wang, Ahmed Louri
2022	J	`jnl`	SGCNAX: A Scalable Graph Convolutional Neural Network Accelerator With Workload Balancing. IEEE Trans. Parallel Distributed Syst. Jiajun Li, Hao Zheng, Ke Wang, Ahmed Louri
2022	A*	`conf`	SPACX: Silicon Photonics-based Scalable Chiplet Accelerator for DNN Inference. HPCA Yuan Li, Ahmed Louri, Avinash Karanth
2022	J	`jnl`	SPRINT: A High-Performance, Energy-Efficient, and Scalable Chiplet-Based Accelerator With Photonic Interconnects for CNN Inference. IEEE Trans. Parallel Distributed Syst. Yuan Li, Ahmed Louri, Avinash Karanth
2022	J	`jnl`	SecureNoC: A Learning-Enabled, High-Performance, Energy-Efficient, and Secure On-Chip Communication Framework Design. IEEE Trans. Sustain. Comput. Ke Wang, Hao Zheng, Yuan Li, Ahmed Louri
2021	J	`jnl`	ALPHA: A Learning-Enabled High-Performance Network-on-Chip Router Design for Heterogeneous Manycore Architectures. IEEE Trans. Sustain. Comput. Yuan Li, Ahmed Louri
2021	A*	`conf`	Adapt-NoC: A Flexible Network-on-Chip Design for Heterogeneous Manycore Architectures. HPCA Hao Zheng, Ke Wang, Ahmed Louri
2021	A*	`conf`	Albireo: Energy-Efficient Acceleration of Convolutional Neural Networks via Silicon Photonics. ISCA Kyle Shiflett, Avinash Karanth, Razvan C. Bunescu, Ahmed Louri
2021	—	`conf`	Bitwise Neural Network Acceleration Using Silicon Photonics. ACM Great Lakes Symposium on VLSI Kyle Shiflett, Avinash Karanth, Ahmed Louri, Razvan C. Bunescu
2021	A*	`conf`	CSCNN: Algorithm-hardware Co-design for CNN Accelerators using Centrosymmetric Filters. HPCA Jiajun Li, Ahmed Louri, Avinash Karanth, Razvan C. Bunescu
2021	A*	`conf`	GCNAX: A Flexible and Energy-efficient Accelerator for Graph Convolutional Neural Networks. HPCA Jiajun Li, Ahmed Louri, Avinash Karanth, Razvan C. Bunescu
2021	J	`jnl`	Reduced Precision Redundancy for Reliable Processing of Data. IEEE Trans. Emerg. Top. Comput. Shanshan Liu, Ke Chen, Pedro Reviriego, Weiqiang Liu, Ahmed Louri, Fabrizio Lombardi
2021	A*	`conf`	Scaling Deep-Learning Inference with Chiplet-based Architecture and Photonic Interconnects. DAC Yuan Li, Ahmed Louri, Avinash Karanth
2021	J	`jnl`	Stochastic Dividers for Low Latency Neural Networks. IEEE Trans. Circuits Syst. I Regul. Pap. Shanshan Liu, Xiaochen Tang, Farzad Niknia, Pedro Reviriego, Weiqiang Liu, Ahmed Louri, Fabrizio Lombardi
2020	—	`conf`	4-Input NAND and NOR Gates Based on Two Ambipolar Schottky Barrier FinFETs. ICECS Talha Furkan Canan, Savas Kaya, Avinash Karanth, Ahmed Louri
2020	A*	`conf`	A Versatile and Flexible Chiplet-based System Design for Heterogeneous Manycore Architectures. DAC Hao Zheng, Ke Wang, Ahmed Louri
2020	J	`jnl`	An Approximate Communication Framework for Network-on-Chips. IEEE Trans. Parallel Distributed Syst. Yuechen Chen, Ahmed Louri
2020	J	`jnl`	CURE: A High-Performance, Low-Power, and Reliable Network-on-Chip Design Using Reinforcement Learning. IEEE Trans. Parallel Distributed Syst. Ke Wang, Ahmed Louri
2020	A	`conf`	DozzNoC: Reducing Static and Dynamic Energy in NoCs with Low-latency Voltage Regulators using Machine Learning. IPDPS Mark Clark, Yingping Chen, Avinash Karanth, Dongsheng Brian Ma, Ahmed Louri
2020	J	`jnl`	Hardware-Level Thread Migration to Reduce On-Chip Data Movement Via Reinforcement Learning. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Quintin Fettes, Avinash Karanth, Razvan C. Bunescu, Ahmed Louri, Kyle Shiflett
2020	J	`jnl`	Learning-Based Quality Management for Approximate Communication in Network-on-Chips. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Yuechen Chen, Ahmed Louri
2020	A*	`conf`	PIXEL: Photonic Neural Network Accelerator. HPCA Kyle Shiflett, Dylan Wright, Avinash Karanth, Ahmed Louri
2020	J	`jnl`	State of the Journal. IEEE Trans. Computers Ahmed Louri
2020	J	`jnl`	TSA-NoC: Learning-Based Threat Detection and Mitigation for Secure Network-on-Chip Architecture. IEEE Micro Ke Wang, Hao Zheng, Ahmed Louri
2019	A*	`conf`	An Energy-Efficient Network-on-Chip Design using Reinforcement Learning. DAC Hao Zheng, Ahmed Louri
2019	A	`conf`	An online quality management framework for approximate communication in network-on-chips. ICS Yuechen Chen, Ahmed Louri
2019	J	`jnl`	Dynamic Voltage and Frequency Scaling in NoCs With Supervised and Reinforcement Learning Techniques. Computer Quintin Fettes, Mark Clark, Razvan C. Bunescu, Avinash Karanth, Ahmed Louri
2019	J	`jnl`	Dynamic Voltage and Frequency Scaling in NoCs with Supervised and Reinforcement Learning Techniques. IEEE Trans. Computers Quintin Fettes, Mark Clark, Razvan C. Bunescu, Avinash Karanth, Ahmed Louri
2019	J	`jnl`	Editorial from the Incoming Editor-in-Chief. IEEE Trans. Computers Ahmed Louri
2019	A	`conf`	High-performance, Energy-efficient, Fault-tolerant Network-on-Chip Design Using Reinforcement Learnin. DATE Ke Wang, Ahmed Louri, Avinash Karanth, Razvan C. Bunescu
2019	A*	`conf`	IntelliNoC: a holistic design framework for energy-efficient and reliable on-chip communication for manycores. ISCA Ke Wang, Ahmed Louri, Avinash Karanth, Razvan C. Bunescu
2019	J	`jnl`	Limit of Hardware Solutions for Self-Protecting Fault-Tolerant NoCs. ACM J. Emerg. Technol. Comput. Syst. Ahmed Louri, Jacques Henri Collet, Avinash Karanth
2019	J	`jnl`	Sustainability in Network-on-Chips by Exploring Heterogeneity in Emerging Technologies. IEEE Trans. Sustain. Comput. Avinash Karanth, Savas Kaya, Md. Ashif I. Sikder, Daniel Carbaugh, Soumyasanta Laha, Dominic DiTomaso, Ahmed Louri, Hao Xin, Junqiang Wu
2019	J	`jnl`	Utility-based resource management in an oversubscribed energy-constrained heterogeneous environment executing parallel applications. Parallel Comput. Dylan Machovec, Bhavesh Khemka, Nirmal Kumbhare, Sudeep Pasricha, Anthony A. Maciejewski, Howard Jay Siegel, Ali Akoglu, Gregory A. Koenig, Salim Hariri, Cihan Tunc, Michael Wright, Marcia Hilton, Rajendra Rambharos, Christopher Blandin, Farah Fargo, Ahmed Louri, Neena Imam
2018	—	`conf`	10T and 8T Full Adders Based on Ambipolar XOR Gates with SB-FinFETs. ICECS Talha Furkan Canan, Savas Kaya, Avinash Kodi, Hao Xin, Ahmed Louri
2018	C	`conf`	DEC-NoC: An Approximate Framework Based on Dynamic Error Control with Applications to Energy-Efficient NoCs. ICCD Yuechen Chen, Md Farhadur Reza, Ahmed Louri
2018	J	`jnl`	EZ-Pass: An Energy & Performance-Efficient Power-Gating Router Architecture for Scalable NoCs. IEEE Comput. Archit. Lett. Hao Zheng, Ahmed Louri
2018	A*	`conf`	Extending the Power-Efficiency and Performance of Photonic Interconnects for Heterogeneous Multicores with Machine Learning. HPCA Scott Van Winkle, Avinash Karanth Kodi, Razvan C. Bunescu, Ahmed Louri
2018	A*	`conf`	LEAD: learning-enabled energy-aware dynamic voltage/frequency scaling in NoCs. DAC Mark Clark, Avinash Kodi, Razvan C. Bunescu, Ahmed Louri
2018	A	`conf`	Scalable Power-Efficient Kilo-Core Photonic-Wireless NoC Architectures. IPDPS Avinash Kodi, Kyle Shifflet, Savas Kaya, Soumyasanta Laha, Ahmed Louri
2018	—	`conf`	Sub-THz Tunable Push-Push Oscillators with FinFETs for Wireless NoCs. MWSCAS Yunus Kelestemur, Soumyasanta Laha, Savas Kaya, Avinash Kodi, Hao Xin, Ahmed Louri
2017	A	`conf`	Machine learning enabled power-aware Network-on-Chip design. DATE Dominic DiTomaso, Md. Ashif I. Sikder, Avinash Karanth Kodi, Ahmed Louri
2017	—	`conf`	Ultra-compact sub-10nm logic circuits based on ambipolar SB-FinFETs. MWSCAS Talha Furkan Canan, Savas Kaya, Avinash Kodi, Hao Xin, Ahmed Louri
2016	J	`jnl`	A Methodology for Cognitive NoC Design. IEEE Comput. Archit. Lett. Wo-Tak Wu, Ahmed Louri
2016	—	`conf`	Design of high bandwidth photonic NoC architectures using optical multilevel signaling. NOCS Tzyy-Juin Kao, Ahmed Louri
2016	A*	`conf`	Dynamic error mitigation in NoCs using intelligent prediction techniques. MICRO Dominic DiTomaso, Travis Boraten, Avinash Kodi, Ahmed Louri
2016	—	`conf`	Reconfigurable Optical and Wireless (R-OWN) Network-on-Chip for High Performance Computing. NANOCOM Md. Ashif I. Sikder, Avinash Karanth Kodi, Ahmed Louri
2016	J	`jnl`	Shield: A Reliable Network-on-Chip Router Architecture for Chip Multiprocessors. IEEE Trans. Parallel Distributed Syst. Pavan Poluri, Ahmed Louri
2015	J	`jnl`	A Soft Error Tolerant Network-on-Chip Router Pipeline for Multi-Core Systems. IEEE Comput. Archit. Lett. Pavan Poluri, Ahmed Louri
2015	—	`conf`	OWN: Optical and Wireless Network-on-Chip for Kilo-core Architectures. Hot Interconnects Md. Ashif I. Sikder, Avinash Karanth Kodi, Matthew Kennedy, Savas Kaya, Ahmed Louri
2015	J	`jnl`	Resilient and Power-Efficient Multi-Function Channel Buffers in Network-on-Chip Architectures. IEEE Trans. Computers Dominic DiTomaso, Avinash Karanth Kodi, Ahmed Louri, Razvan C. Bunescu
2014	A	`conf`	An Improved Router Design for Reliable On-Chip Networks. IPDPS Pavan Poluri, Ahmed Louri
2014	A*	`conf`	QORE: A fault tolerant network-on-chip architecture with power-efficient quad-function channel (QFC) buffers. HPCA Dominic DiTomaso, Avinash Karanth Kodi, Ahmed Louri
2014	J	`jnl`	Three-Dimensional Stacked Nanophotonic Network-on-Chip Architecture with Minimal Reconfiguration. IEEE Trans. Computers Randy Morris, Avinash Karanth Kodi, Ahmed Louri, Ralph D. Whaley
2014	J	`jnl`	Workload assignment considering NBTI degradation in multicore systems. ACM J. Emerg. Technol. Comput. Syst. Jin Sun, Roman L. Lysecky, Karthik Shankar, Avinash Karanth Kodi, Ahmed Louri, Janet Roveda
2013	—	`conf`	Design of a Concentrated Torus Topology with Channel Buffers and Efficient Crossbars in NoCs. IPDPS Workshops Dominic DiTomaso, Randy Morris, Evan Jolley, Ashwini Sarathy, Ahmed Louri, Avinash Karanth Kodi
2013	—	`conf`	Evaluating the scalability and performance of 3D stacked reconfigurable nanophotonic interconnects. SLIP Randy Morris, Avinash Karanth Kodi, Ahmed Louri
2013	J	`jnl`	Extending the Energy Efficiency and Performance With Channel Buffers, Crossbars, and Topology Analysis for Network-on-Chips. IEEE Trans. Very Large Scale Integr. Syst. Dominic DiTomaso, Randy Morris, Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
2013	C	`conf`	Tackling Permanent Faults in the Network-on-Chip Router Pipeline. SBAC-PAD Pavan Poluri, Ahmed Louri
2012	C	`conf`	3D-NoC: Reconfigurable 3D photonic on-chip interconnect for multicores. ICCD Randy Morris, Avinash Karanth Kodi, Ahmed Louri
2012	A*	`conf`	Dynamic Reconfiguration of 3D Photonic Networks-on-Chip for Maximizing Performance and Improving Fault Tolerance. MICRO Randy Morris, Avinash Karanth Kodi, Ahmed Louri
2012	—	`conf`	Evaluation of fault tolerant channel buffers for improving reliability in NoCs. MWSCAS Dominic DiTomaso, Travis Boraten, Avinash Kodi, Ahmed Louri
2011	A	`conf`	Co-design of channel buffers and crossbar organizations in NoCs architectures. ICCAD Avinash Karanth Kodi, Randy Morris, Dominic DiTomaso, Ashwini Sarathy, Ahmed Louri
2011	J	`jnl`	Introduction to the special issue on Networks-on-Chip (NoC) of the Journal of Parallel and Distributed Computing (JPDC). J. Parallel Distributed Comput. Ahmed Louri, Avinash Karanth Kodi
2011	—	`conf`	ROBUST: a new self-healing fault-tolerant NoC router. NoCArc@MICRO Jacques Henri Collet, Ahmed Louri, Vivek Tulsidas Bhat, Pavan Poluri
2010	A*	`conf`	A multilayer nanophotonic interconnection network for on-chip many-core communications. DAC Xiang Zhang, Ahmed Louri
2010	J	`jnl`	Special Issue on Network-on-Chips (NoCs). J. Parallel Distributed Comput. Ahmed Louri, Avinash Karanth Kodi
2010	—	`conf`	Workload capacity considering NBTI degradation in multi-core systems. ASP-DAC Jin Sun, Roman L. Lysecky, Karthik Shankar, Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang
2009	—	`conf`	Adaptive inter-router links for low-power, area-efficient and reliable Network-on-Chip (NoC) architectures. ASP-DAC Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri, Janet Meiling Wang
2009	—	`conf`	Design of energy-efficient channel buffers with router bypassing for network-on-chips (NoCs). ISQED Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang
2009	—	`conf`	NBTI aware workload balancing in multi-core systems. ISQED Jin Sun, Avinash Karanth Kodi, Ahmed Louri, Janet Meiling Wang
2009	—	`conf`	On-Chip photonic interconnects for scalable multi-core architectures. NOCS Avinash Karanth Kodi, Randy Morris, Ahmed Louri, Xiang Zhang
2008	J	`jnl`	Adaptive Channel Buffers in On-Chip Interconnection Networks - A Power and Performance Analysis. IEEE Trans. Computers Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
2008	J	`jnl`	Optisim: A System Simulation Methodology for Optically Interconnected HPC Systems. IEEE Micro Avinash Karanth Kodi, Ahmed Louri
2008	A*	`conf`	iDEAL: Inter-router Dual-Function Energy and Area-Efficient Links for Network-on-Chip (NoC) Architectures. ISCA Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
2007	—	`conf`	Design of adaptive communication channel buffers for low-power area-efficient network-on-chip architecture. ANCS Avinash Karanth Kodi, Ashwini Sarathy, Ahmed Louri
2007	—	`conf`	Implementation of Dynamic Bandwidth Re-allocation in Optical Interconnects using Microring Resonators. Hot Interconnects Chander Kochar, Avinash Karanth Kodi, Ahmed Louri
2007	A	`conf`	Performance adaptive power-aware reconfigurable optical interconnects for high-performance computing (HPC) systems. SC Avinash Karanth Kodi, Ahmed Louri
2007	A	`conf`	Power-Aware Bandwidth-Reconfigurable Optical Interconnects for High-Performance Computing (HPC) Systems. IPDPS Avinash Karanth Kodi, Ahmed Louri
2006	—	`conf`	A New Dynamic Bandwidth Re-Allocation Technique in Optically Interconnected High-Performance Computing Systems. Hot Interconnects Avinash Karanth Kodi, Ahmed Louri
2005	J	`jnl`	Design of a High-Speed Optical Interconnect for Scalable Shared-Memory Multiprocessors. IEEE Micro Avinash Karanth Kodi, Ahmed Louri
2004	A	`conf`	A Scalable Architecture for Distributed Shared Memory Multiprocessors Using Optical Interconnects. IPDPS Avinash Karanth Kodi, Ahmed Louri
2004	J	`jnl`	An Optical Interconnection Network and a Modified Snooping Protocol for the Design of Large-Scale Symmetric Multiprocessors (SMPs). IEEE Trans. Parallel Distributed Syst. Ahmed Louri, Avinash Karanth Kodi
2004	—	`conf`	Design of a high-speed optical interconnect for scalable shared memory multiprocessors. Hot Interconnects Avinash Karanth Kodi, Ahmed Louri
2000	J	`jnl`	A Class of Highly Scalable Optical Crossbar-Connected Interconnection Networks (SOCNs) for Parallel Computing Systems. IEEE Trans. Parallel Distributed Syst. Brian Webb, Ahmed Louri
2000	—	`conf`	The Equivalency Processing Parallel Photonic Integrated Circuit (EP3IC), a Parallel Digital Equivalence Search Module. AIPR Peng Yin Choo, Abram Detofsky, Ahmed Louri
1999	—	`conf`	A Multi-Wavelength Optical Content-Addressable Parallel Processor (MW-OCAPP) for High-Speed Parallel Relational Database Processing: Architectural Concepts and Preliminary Experimental System. IPPS/SPDP Workshops Peng Yin Choo, Abram Detofsky, Ahmed Louri
1998	J	`jnl`	A Spanning Multichannel Linked Hypercube: A Gradually Scalable Optical Interconnection Network for Massively Parallel Computing. IEEE Trans. Parallel Distributed Syst. Ahmed Louri, Brent Weech, Costas Neocleous
1998	B	`conf`	Media Access Protocols For A Scalable Optical Interconnection Network. ICPP Thomas S. Jones, Ahmed Louri
1995	J	`jnl`	A constant-time parallel sorting algorithm and its optical implementation. IEEE Micro Ahmed Louri, James A. Hatch Jr., Jongwhoa Na
1994	J	`jnl`	3D Optical Interconnects for High-Speed Interchip and Interboard Communications. Computer Ahmed Louri, Hongki Sung
1994	J	`jnl`	An Optical Associative Parallel Processor for High-Speed Database Processing. Computer Ahmed Louri, James A. Hatch Jr.
1993	J	`jnl`	A Simulation Environment for Intelligent Machine Architectures. J. Parallel Distributed Comput. Bernard P. Zeigler, Ahmed Louri
1993	—	`conf`	Performance Considerations Relating to the Design of Interconnection Networks for Multiprocessing Systems. ICPP (1) Earl Hokens, Ahmed Louri
1992	—	`conf`	A Compiler Directed Cache Coherence Scheme with Fast and Parallel Explicit Invalidation. ICPP (1) Ahmed Louri, Hongki Sung
1992	A*	`conf`	A new compiler-directed cache coherence scheme for shared memory multiprocessors with fast and parallel explicit invalidation. ISCA Ahmed Louri, Hongki Sung
1992	A*	`conf`	Parallel electro-optical rule-based system for fast execution of expert systems. ISCA Ahmed Louri, Jongwhoa Na
1991	—	`conf`	An Optical Content-Adressable Parallel Processor for Fast Searching and Retrieving. PARLE (1) Ahmed Louri
1991	—	`conf`	Design and Evaluation of Fault-Tolerant Interleaved Memory Systems. ICPP (1) Sy-Yen Kuo, Ahmed Louri, Sheng-Chiech Liang
1991	—	`conf`	Design of an Optical Content-Addressable Parallel Processor with Applications to Fast Searching and Information Retrieval. IPPS Ahmed Louri
1991	J	`jnl`	Three-dimensional optical architecture and data-parallel algorithms for massively parallel computing. IEEE Micro Ahmed Louri
1990	—	`conf`	A Symbolic Substitution Based Parallel Architecture and Algorithms for High-speed Parallel Processing. ACM Conference on Computer Science Ahmed Louri
1988	A*	`conf`	A Bit-Plane Architecture for Optical Computing with Two-Dimensional Symbolic Substitution. ISCA Ahmed Louri, Kai Hwang
1988	—	`conf`	Optical Arithmetic Using Signed-Digit Symbolic Substitution. ICPP (1) Kai Hwang, Ahmed Louri
1987	—	`conf`	A Parallel Architecture for Optical Computing. PP Ahmed Louri, Kai Hwang