Ahmed Hemani - RankMe

175 papers A* 3A 9B 3C 27Misc 19Journal 49Unranked 64

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	'1'-bit Count-based Sorting Unit to Reduce Link Power in DNN Accelerators. CoRR Ruichi Han, Yizhi Chen, Tong Lei, Jordi Altayó González, Ahmed Hemani
2026	J	`jnl`	Late Breaking Results: Quamba-SE: Soft-edge Quantizer for Activations in State Space Models. CoRR Yizhi Chen, Ahmed Hemani
2026	J	`jnl`	SIMBRAIN: A nonidealities-aware simulation framework for spiking neural networks based on memristor crossbars. Neurocomputing Jiawei Xu, Yi Zheng, Ruisi Shen, Ruijia Wang, Jie Li, Deyu Wang, Dimitrios Stathis, Lirong Zheng, Zhuo Zou, Ahmed Hemani
2025	J	`jnl`	MemMIMO: A Simulation Framework for Memristor-Based Massive MIMO Acceleration. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jiawei Xu, Yi Zheng, Dimitrios Stathis, Ruijia Wang, Ruisi Shen, Lirong Zheng, Zhuo Zou, Ahmed Hemani
2025	C	`conf`	Modeling and Scheduling of Composable Instruction Set. DSD Yu Yang, Paul Delestrac, Ahmed Hemani
2025	J	`jnl`	Scalable Multi-FPGA HPC Architecture for Associative Memory System. IEEE Trans. Biomed. Circuits Syst. Deyu Wang, Xiaoze Yan, Yu Yang, Dimitrios Stathis, Ahmed Hemani, Anders Lansner, Jiawei Xu, Li-Rong Zheng, Zhuo Zou
2024	J	`jnl`	Application Level Synthesis: Creating Matrix-Matrix Multiplication Library: A Case Study. IEEE Access Pudi Dhilleswararao, Yu Yang, Dimitrios Stathis, Sunil Kumar Prajapati, Srinivas Boppu, Ahmed Hemani, Linga Reddy Cenkeramaddi
2024	J	`jnl`	Automating functional unit and register binding for synchoros CGRA platform. Des. Autom. Embed. Syst. Pudi Dhilleswararao, Utsav Tiwari, Srinivas Boppu, Yu Yang, Ahmed Hemani
2024	J	`jnl`	CIS: Composable Instruction Set for Streaming Applications: Design, Modeling, and Scheduling. CoRR Yu Yang, Jordi Altayó González, Ahmed Hemani
2024	J	`jnl`	DUDE: Decryption, Unpacking, Deobfuscation, and Endian Conversion Framework for Embedded Devices Firmware. IEEE Trans. Dependable Secur. Comput. Haider Abbas, Muhammad Shahzad, Maliha Safdar, Ahmed Hemani
2024	C	`conf`	Exploration of Custom Floating-Point Formats: A Systematic Approach. DSD Saba Yousefzadeh, Yu Yang, Astile Peter, Dimitrios Stathis, Ahmed Hemani
2024	B	`conf`	FPGA-Based HPC for Associative Memory System. ASPDAC Deyu Wang, Yuning Wang, Yu Yang, Dimitrios Stathis, Ahmed Hemani, Anders Lansner, Jiawei Xu, Li-Rong Zheng, Zhuo Zou
2024	J	`jnl`	Integer Linear Programming-Based Simultaneous Scheduling and Binding for SiLago Framework. IEEE Access Pudi Dhilleswararao, Shivam Malviya, Srinivas Boppu, Yu Yang, Ahmed Hemani, Linga Reddy Cenkeramaddi
2024	J	`jnl`	Modeling Cycle-to-Cycle Variation in Memristors for In-Situ Unsupervised Trace-STDP Learning. IEEE Trans. Circuits Syst. II Express Briefs Jiawei Xu, Yi Zheng, Feng Li, Dimitrios Stathis, Ruisi Shen, Haoming Chu, Anders Lansner, Lirong Zheng, Zhuo Zou, Ahmed Hemani
2023	J	`jnl`	A Memristor-Based Learning Engine for Synaptic Trace-Based Online Learning. IEEE Trans. Biomed. Circuits Syst. Deyu Wang, Jiawei Xu, Feng Li, Lianhao Zhang, Chengwei Cao, Dimitrios Stathis, Anders Lansner, Ahmed Hemani, Lirong Zheng, Zhuo Zou
2023	J	`jnl`	Clock tree generation by abutment in synchoros VLSI design. Microprocess. Microsystems Dimitrios Stathis, Panagiotis Chaourani, Syed M. A. H. Jafri, Ahmed Hemani
2023	Misc	`conf`	DRRA-based Reconfigurable Architecture for Mixed-Radix FFT. VLSID Reeshita Kallapu, Dimitrios Stathis, Srinivas Boppu, Ahmed Hemani
2023	—	`conf`	Efficient Implementation of 2-D Convolution on DRRA and DiMArch Architectures. HEART Pudi Dhilleswararao, Rajeev Ryansh, Srinivas Boppu, Yu Yang, Ahmed Hemani
2023	—	`conf`	Implementation of Image Averaging on DRRA and DiMArch Architectures. SBCCI Pudi Dhilleswararao, Vamsi Goudu, Srinivas Boppu, Ritika Ratnu, Ahmed Hemani
2023	C	`conf`	Implementation of Sobel Edge Detection on DRRA and DiMArch Architectures. DSD Pudi Dhilleswararao, Rajeev Ryansh, Vamsi Goudu, Srinivas Boppu, Ahmed Hemani
2023	—	`conf`	Optimizing Self-Organizing Maps for Bacterial Genome Identification on Parallel Ultra-Low-Power Platforms. ICECS Seyed Ahmad Mirsalari, Saba Yousefzadeh, Giuseppe Tagliavini, Dimitrios Stathis, Ahmed Hemani
2023	—	`conf`	Optoelectronic Memristor Model for Optical Synaptic Circuit of Spiking Neural Networks. NEWCAS Jiawei Xu, Yi Zheng, Chenxu Sheng, Yichen Cai, Dimitrios Stathis, Ruisi Shen, Lirong Zheng, Zhuo Zou, Laigui Hu, Ahmed Hemani
2022	J	`jnl`	MOHAQ: Multi-Objective Hardware-Aware Quantization of recurrent neural networks. J. Syst. Archit. Nesma M. Rezk, Tomas Nordström, Dimitrios Stathis, Zain Ul-Abdin, Eren Erdal Aksoy, Ahmed Hemani
2022	—	`conf`	Memristor-Based In-Circuit Computation for Trace-Based STDP. AICAS Deyu Wang, Jiawei Xu, Feng Li, Lianhao Zhang, Yuning Wang, Anders Lansner, Ahmed Hemani, Lirong Zheng, Zhuo Zou
2022	A	`conf`	Reducing the Configuration Overhead of the Distributed Two-level Control System. DATE Yu Yang, Dimitrios Stathis, Ahmed Hemani
2022	J	`jnl`	Vesyla-II: An Algorithm Library Development Tool for Synchoros VLSI Design Style. CoRR Yu Yang, Ahmed Hemani
2021	—	`conf`	A Memristor Model with Concise Window Function for Spiking Brain-Inspired Computation. AICAS Jiawei Xu, Deyu Wang, Feng Li, Lianhao Zhang, Dimitrios Stathis, Yu Yang, Yi Jin, Anders Lansner, Ahmed Hemani, Zhuo Zou, Li-Rong Zheng
2021	A	`conf`	Approximate computation of post-synaptic spikes reduces bandwidth to synaptic storage in a model of cortex. DATE Dimitrios Stathis, Yu Yang, Ahmed Hemani, Anders Lansner
2021	—	`conf`	Clock Tree Generation by Abutment in Synchoros VLSI Design. NorCAS Dimitrios Stathis, Panagiotis Chaourani, Syed M. A. H. Jafri, Ahmed Hemani
2021	—	`conf`	Design and Implementation of Optimized Register File for Streaming Applications. VDAT Ayazulla Khan Patan, Dimitrios Stathis, Pudi Dhilleswararao, Yu Yang, Srinivas Boppu, Ahmed Hemani
2021	J	`jnl`	Multi-objective Recurrent Neural Networks Optimization for the Edge - a Quantization-based Approach. CoRR Nesma M. Rezk, Tomas Nordström, Dimitrios Stathis, Zain Ul-Abdin, Eren Erdal Aksoy, Ahmed Hemani
2021	J	`jnl`	Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators. ACM Trans. Archit. Code Optim. Syed Mohammad Asad Hassan Jafri, Hasan Hassan, Ahmed Hemani, Onur Mutlu
2021	C	`conf`	Scheduling Persistent and Fully Cooperative Instructions. DSD Yu Yang, Ahmed Hemani, Kolin Paul
2021	Misc	`conf`	Scheduling Persistent and Fully Cooperative Instructions. FCCM Yu Yang, Ahmed Hemani, Kolin Paul
2021	J	`jnl`	Synthesis of Predictable Global NoC by Abutment in Synchoros VLSI Design. CoRR Jordi Altayó González, Dimitrios Stathis, Ahmed Hemani
2021	—	`conf`	Synthesis of predictable global NoC by abutment in synchoros VLSI design. NOCS Jordi Altayó González, Dimitrios Stathis, Ahmed Hemani
2020	—	`conf`	A FPGA-based Hardware Accelerator for Bayesian Confidence Propagation Neural Network. NorCAS Lizheng Liu, Deyu Wang, Yuning Wang, Anders Lansner, Ahmed Hemani, Yu Yang, Xiaoming Hu, Zhuo Zou, Lirong Zheng
2020	J	`jnl`	Guest Editorial: Special Issue on Architectures and Design Methods for Neural Networks. J. Signal Process. Syst. Ahmed Hemani, Muhammad Shafique, Kolin Paul
2020	A*	`conf`	NACU: A Non-Linear Arithmetic Unit for Neural Networks. DAC Guido Baccelli, Dimitrios Stathis, Ahmed Hemani, Maurizio Martina
2020	J	`jnl`	eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex. J. Signal Process. Syst. Dimitrios Stathis, Chirag Sudarshan, Yu Yang, Matthias Jung, Christian Weis, Ahmed Hemani, Anders Lansner, Norbert Wehn
2019	—	`conf`	Approximate Computing Applied to Bacterial Genome Identification using Self-Organizing Maps. ISVLSI Dimitrios Stathis, Yu Yang, Saurabh Tewari, Ahmed Hemani, Kolin Paul, Manfred G. Grabherr, Rafi Ahmad
2019	J	`jnl`	Configurable FFT Processor Using Dynamically Reconfigurable Resource Arrays. J. Signal Process. Syst. Muhammad Ali Shami, Muhammad Adeel Tajammul, Ahmed Hemani
2019	J	`jnl`	Refresh Triggered Computation: Improving the Energy Efficiency of Convolutional Neural Network Accelerators. CoRR Syed M. A. H. Jafri, Hasan Hassan, Ahmed Hemani, Onur Mutlu
2019	J	`jnl`	Regional Clock Tree Generation by Abutment in Synchoros VLSI Design. CoRR Dimitrios Stathis, Panagiotis Chaourani, Syed M. A. H. Jafri, Ahmed Hemani
2019	J	`jnl`	eBrainII: A 3 kW Realtime Custom 3D DRAM integrated ASIC implementation of a Biologically Plausible Model of a Human Scale Cortex. CoRR Dimitrios Stathis, Chirag Sudarshan, Yu Yang, Matthias Jung, Syed Mohammad Asad Hassan Jafri, Christian Weis, Ahmed Hemani, Anders Lansner, Norbert Wehn
2018	—	`conf`	RiBoSOM: rapid bacterial genome identification using self-organizing map implemented on the synchoros SiLago platform. SAMOS Yu Yang, Dimitrios Stathis, Prashant Sharma, Kolin Paul, Ahmed Hemani, Manfred G. Grabherr, Rafi Ahmad
2017	J	`jnl`	3D-Stacked Many-Core Architecture for Biological Sequence Analysis Problems. Int. J. Parallel Program. Pei Liu, Ahmed Hemani, Kolin Paul, Christian Weis, Matthias Jung, Norbert Wehn
2017	J	`jnl`	A Customized Many-Core Hardware Acceleration Platform for Short Read Mapping Problems Using Distributed Memory Interface with 3D-Stacked Architecture. J. Signal Process. Syst. Pei Liu, Ahmed Hemani, Kolin Paul, Christian Weis, Matthias Jung, Norbert Wehn
2017	—	`conf`	Can a reconfigurable architecture beat ASIC as a CNN accelerator? SAMOS Syed M. A. H. Jafri, Ahmed Hemani, Dimitrios Stathis
2017	A	`conf`	MOCHA: Morphable Locality and Compression Aware Architecture for Convolutional Neural Networks. IPDPS Syed Mohammad Asad Hassan Jafri, Ahmed Hemani, Kolin Paul, Naeem Abbas
2017	—	`conf`	MTP-Caffe: Memory, Timing, and Power aware tool for mapping CNNs to GPUs. PARMA-DITAM@HiPEAC Yu Yang, Syed M. A. H. Jafri, Ahmed Hemani, Dimitrios Stathis
2017	J	`jnl`	Quality-of-service-aware adaptation scheme for multi-core protocol processing architecture. Microprocess. Microsystems Mohammad Badawi, Zhonghai Lu, Ahmed Hemani
2017	C	`conf`	SPEED: Open-Source Framework to Accelerate Speech Recognition on Embedded GPUs. DSD Syed Mohammad Asad Hassan Jafri, Ahmed Hemani, Leonardo Intesa
2017	—	`conf`	SiLago-CoG: Coarse-Grained Grid-Based Design for Near Tape-Out Power Estimation Accuracy at High Level. ISVLSI Syed Mohammad Asad Hassan Jafri, Nasim Farahini, Ahmed Hemani
2017	—	`conf`	Synchoricity and NOCs could make Billion Gate Custom Hardware Centric SOCs Affordable. NOCS Ahmed Hemani, Syed Mohammad Asad Hassan Jafri, Shayesteh Masoumian
2016	C	`conf`	Elastic Management and QoS Provisioning Scheme for Adaptable Multi-core Protocol Processing Architecture. DSD Mohammad Badawi, Zhonghai Lu, Ahmed Hemani
2016	J	`jnl`	Gaussian Random Number Generation: A Survey on Hardware Architectures. ACM Comput. Surv. Jamshaid Sarwar Malik, Ahmed Hemani
2016	J	`jnl`	Polymorphic Configuration Architecture for CGRAs. IEEE Trans. Very Large Scale Integr. Syst. Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Ahmed Hemani, Kolin Paul, Juha Plosila, Peeter Ellervee, Hannu Tenhunen
2016	C	`conf`	Service-Guaranteed Multi-port Packet Memory for Parallel Protocol Processing Architecture. PDP Mohammad Badawi, Zhonghai Lu, Ahmed Hemani
2016	—	`conf`	The SiLago Method: Next Generation VLSI Architectures and Design Methods. MES@ISCA Ahmed Hemani
2016	J	`jnl`	TransMap: Transformation Based Remapping and Parallelism for High Utilization and Energy Efficiency in CGRAs. IEEE Trans. Computers Syed M. A. H. Jafri, Masoud Daneshtalab, Naeem Abbas, Guillermo Serrano Leon, Ahmed Hemani
2016	—	`conf`	TransMem: A memory architecture to support dynamic remapping and parallelism in low power high performance CGRAs. PATMOS Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Ahmed Hemani, Peeter Ellervee
2015	—	`conf`	3D-stacked many-core architecture for biological sequence analysis problems. SAMOS Pei Liu, Ahmed Hemani, Kolin Paul
2015	J	`jnl`	Architecture and Implementation of Dynamic Parallelism, Voltage and Frequency Scaling (PVFS) on CGRAs. ACM J. Emerg. Technol. Comput. Syst. Syed M. A. H. Jafri, Ozan Ozbag, Nasim Farahini, Kolin Paul, Ahmed Hemani, Juha Plosila, Hannu Tenhunen
2015	—	`conf`	Atomic stream computation unit based on micro-thread level parallelism. ASAP Nasim Farahini, Ahmed Hemani
2015	Misc	`conf`	DyMeP: An Infrastructure to Support Dynamic Memory Binding for Runtime Mapping in CGRAs. VLSID Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Peeter Ellervee, Ahmed Hemani, Hannu Tenhunen, Juha Plosila
2015	C	`conf`	FIST: A Framework to Interleave Spiking Neural Networks on CGRAs. PDP Tuan Ngyen, Syed M. A. H. Jafri, Masoud Daneshtalab, Ahmed Hemani, Sergei Dytckov, Juha Plosila, Hannu Tenhunen
2015	—	`conf`	Physical design aware system level synthesis of hardware. SAMOS Nasim Farahini, Ahmed Hemani, Hasan Sohofi, Shuo Li
2015	J	`jnl`	Revisiting Central Limit Theorem: Accurate Gaussian Random Number Generation in VLSI. IEEE Trans. Very Large Scale Integr. Syst. Jamshaid Sarwar Malik, Ahmed Hemani, Jameel Nawaz Malik, Ben Slimane, Nasirud Din Gohar
2015	J	`jnl`	TEA: Timing and Energy Aware compression architecture for Efficient Configuration in CGRAs. Microprocess. Microsystems Syed M. A. H. Jafri, Masoud Daneshtalab, Ahmed Hemani, Naeem Abbas, Muhammad Ali Awan, Juha Plosila
2014	—	`conf`	A many-core hardware acceleration platform for short read mapping problem using distributed memory interface with 3D-stacked architecture. ISSoC Pei Liu, Ahmed Hemani, Kolin Paul
2014	—	`conf`	A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brain. ASP-DAC Nasim Farahini, Ahmed Hemani, Anders Lansner, Fabien Clermidy, Christer Svensson
2014	Misc	`conf`	Accurate and Efficient Three Level Design Space Exploration Based on Constraints Satisfaction Optimization Problem Solver. FCCM Shuo Li, Ahmed Hemani
2014	A	`conf`	Case Study: Constraint Programming in a System Level Synthesis Framework. CP Shuo Li, Ahmed Hemani
2014	Misc	`conf`	Customizable Compression Architecture for Efficient Configuration in CGRAs. FCCM Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Peeter Ellervee, Juha Plosila, Hannu Tenhunen
2014	—	`conf`	Customizable coarse-grained energy-efficient reconfigurable packet processing architecture. ASAP Mohammad Badawi, Ahmed Hemani, Zhonghai Lu
2014	—	`conf`	Customization methodology of a Coarse Grained Reconfigurable architecture. NORCHIP Siavoosh Payandeh Azad, Nasim Farahini, Ahmed Hemani
2014	—	`conf`	Exploring Spiking Neural Network on Coarse-Grain Reconfigurable Architectures. MES Hassan Anwar, Syed M. A. H. Jafri, Sergei Dytckov, Masoud Daneshtalab, Masoumeh Ebrahimi, Ahmed Hemani, Juha Plosila, Giovanni Beltrame, Hannu Tenhunen
2014	J	`jnl`	Low-Latency Maximal-Throughput Communication Interfaces for Rationally Related Clock Domains. IEEE Trans. Very Large Scale Integr. Syst. Jean-Michel Chabloz, Ahmed Hemani
2014	C	`conf`	Morphable Compression Architecture for Efficient Configuration in CGRAs. DSD Syed Mohammad Asad Hassan Jafri, Muhammad Adeel Tajammul, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Peeter Ellervee, Juha Plosila, Hannu Tenhunen
2014	—	`conf`	NeuroCGRA: A CGRA with support for neural networks. HPCS Syed M. A. H. Jafri, Tuan Nguyen Gia, Sergei Dytckov, Masoud Daneshtalab, Ahmed Hemani, Juha Plosila, Hannu Tenhunen
2014	J	`jnl`	Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric. Microprocess. Microsystems Nasim Farahini, Ahmed Hemani, Hasan Sohofi, Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Kolin Paul
2014	J	`jnl`	Private reliability environments for efficient fault-tolerance in CGRAs. Des. Autom. Embed. Syst. Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
2014	—	`conf`	RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAs. ICSAMOS Syed M. A. H. Jafri, Guilermo Serrano, Junaid Iqbal, Masoud Daneshtalab, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
2014	J	`jnl`	Special issue on many-core embedded systems. Microprocess. Microsystems Masoud Daneshtalab, Maurizio Palesi, Juha Plosila, Ahmed Hemani
2014	—	`conf`	Spiking brain models: Computation, memory and communication constraints for custom hardware implementation. ASP-DAC Anders Lansner, Ahmed Hemani, Nasim Farahini
2014	C	`conf`	Three-Dimensional Design Space Exploration for System Level Synthesis. DSD Shuo Li, Ahmed Hemani
2014	B	`conf`	TransPar: Transformation based dynamic Parallelism for low power CGRAs. FPL Syed M. A. H. Jafri, Guilermo Serrano, Masoud Daneshtalab, Naeem Abbas, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
2013	C	`conf`	39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation. ISCAS Nasim Farahini, Shuo Li, Muhammad Adeel Tajammul, Muhammad Ali Shami, Guo Chen, Ahmed Hemani, Wei Ye
2013	—	`conf`	A code generation method for system-level synthesis on ASIC, FPGA and manycore CGRA. MES Shuo Li, Jamshaid Sarwar Malik, Shaoteng Liu, Ahmed Hemani
2013	C	`conf`	Distributed Runtime Computation of Constraints for Multiple Inner Loops. DSD Nasim Farahini, Ahmed Hemani, Kolin Paul
2013	C	`conf`	Energy-Aware Fault-Tolerant CGRAs Addressing Application with Different Reliability Needs. DSD Syed M. A. H. Jafri, Stanislaw J. Piestrak, Kolin Paul, Ahmed Hemani, Juha Plosila, Hannu Tenhunen
2013	—	`conf`	Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells. ISQED Syed M. A. H. Jafri, Ozan Bag, Ahmed Hemani, Nasim Farahini, Kolin Paul, Juha Plosila, Hannu Tenhunen
2013	J	`jnl`	Energy-aware fault-tolerant network-on-chips for addressing multiple traffic classes. Microprocess. Microsystems Syed M. A. H. Jafri, Liang Guang, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
2013	—	`conf`	Energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAs. ICSAMOS Syed M. A. H. Jafri, Muhammad Adeel Tajammul, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
2013	Misc	`conf`	Global Control and Storage Synthesis for a System Level Synthesis Approach. FCCM Shuo Li, Nasim Farahini, Ahmed Hemani
2013	C	`conf`	Global Interconnect and Control Synthesis in System Level Architectural Synthesis Framework. DSD Shuo Li, Ahmed Hemani
2013	C	`conf`	High performance 3D-FFT implementation. ISCAS U. Nidhi, Kolin Paul, Ahmed Hemani, Anshul Kumar
2013	—	`conf`	Implementation and evaluation of configuration scrubbing on CGRAs: A case study. ISSoC Syed M. A. H. Jafri, Stanislaw J. Piestrak, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
2013	—	`conf`	Memory allocation and optimization in system-level architectural synthesis. ReCoSoC Shuo Li, Ahmed Hemani
2013	J	`jnl`	Power-aware dynamic memory management on many-core platforms utilizing DVFS. ACM Trans. Embed. Comput. Syst. Iraklis Anagnostopoulos, Jean-Michel Chabloz, Ioannis Koutras, Alexandros Bartzas, Ahmed Hemani, Dimitrios Soudris
2013	—	`conf`	Private configuration environments (PCE) for efficient reconfiguration, in CGRAs. ASAP Muhammad Adeel Tajammul, Syed M. A. H. Jafri, Ahmed Hemani, Juha Plosila, Hannu Tenhunen
2013	—	`ed.`	Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, MES'2013, Held in conjunction with the 40th Annual IEEE/ACM International Symposium on Computer Architecture, ISCA 2013, June 24, 2013. MES Masoud Daneshtalab, Ahmed Hemani, Maurizio Palesi
2013	Misc	`conf`	System level synthesis of hardware for DSP applications using pre-characterized function implementations. CODES+ISSS Shuo Li, Nasim Farahini, Ahmed Hemani, Kathrin Rosvall, Ingo Sander
2013	—	`conf`	Unifying CORDIC and Box-Muller algorithms: An accurate and efficient Gaussian Random Number generator. ASAP Jamshaid Sarwar Malik, Ahmed Hemani, Nasirud Din Gohar
2012	—	`conf`	A pragma based approach for mapping MATLAB applications on a coarse grained reconfigurable architecture. SBCCI Omer Malik, Ahmed Hemani
2012	—	`conf`	Classification of Massively Parallel Computer Architectures. IPDPS Workshops Muhammad Ali Shami, Ahmed Hemani
2012	J	`jnl`	Effort, resources, and abstraction vs performance in high-level synthesis: finding new answers to an old question. SIGARCH Comput. Archit. News Jamshaid Sarwar Malik, Paolo Palazzari, Ahmed Hemani
2012	C	`conf`	Energy-Aware Fault-Tolerant Network-on-Chips for Addressing Multiple Traffic Classes. DSD Syed M. A. H. Jafri, Liang Guang, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
2012	—	`conf`	Improved Bioinformatics Processing Unit for Multiple Applications. IPDPS Workshops Pei Liu, Ahmed Hemani, Kolin Paul
2012	Misc	`conf`	Low-Latency No-Handshake GALS Interfaces for Fast-Receiver Links. VLSI Design Jean-Michel Chabloz, Ahmed Hemani
2012	—	`conf`	Segmented Bus Based Path Setup Scheme for a Distributed Memory Architecture. MCSoC Muhammad Adeel Tajammul, Muhammad Ali Shami, Ahmed Hemani
2012	—	`conf`	Self-adaptive Noc Power Management with Dual-level Agents - Architecture and Implementation. PECCS Syed M. A. H. Jafri, Liang Guang, Axel Jantsch, Kolin Paul, Ahmed Hemani, Hannu Tenhunen
2011	—	`conf`	A Coarse-Grained Reconfigurable Processor for Sequencing and Phylogenetic Algorithms in Bioinformatics. ReConFig Pei Liu, Fatemeh O. Ebrahim, Ahmed Hemani, Kolin Paul
2011	C	`conf`	A GALS Network-on-Chip based on rationally-related frequencies. ICCD Jean-Michel Chabloz, Ahmed Hemani
2011	Misc	`conf`	A Library Development Framework for a Coarse Grain Reconfigurable Architecture. VLSI Design Omer Malik, Ahmed Hemani, Muhammad Ali Shami
2011	Misc	`conf`	A Reconfigurable Processor for Phylogenetic Inference. VLSI Design Pei Liu, Ahmed Hemani, Kolin Paul
2011	—	`conf`	A coarse-grained reconfigurable protocol processor. SoC Mohammad Badawi, Ahmed Hemani
2011	—	`conf`	Address generation scheme for a coarse grain reconfigurable architecture. ASAP Muhammad Ali Shami, Ahmed Hemani
2011	J	`jnl`	Addressing Dynamic Issues in Information Security Management. Inf. Manag. Comput. Secur. Haider Abbas, Christer Magnusson, Louise Yngström, Ahmed Hemani
2011	—	`conf`	An efficient hardware implementation of high quality AWGN generator using Box-Muller method. ISCIT Jamshaid Sarwar Malik, Jameel Nawaz Malik, Ahmed Hemani, Nasirud Din Gohar
2011	—	`conf`	Compact generic intermediate representation (CGIR) to enable late binding in coarse grained reconfigurable architectures. FPT Syed M. A. H. Jafri, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
2011	—	`conf`	Compression Based Efficient and Agile Configuration Mechanism for Coarse Grained Reconfigurable Architectures. IPDPS Workshops Syed M. A. H. Jafri, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen
2011	C	`conf`	Generating high tail accuracy Gaussian Random Numbers in hardware using central limit theorem. VLSI-SoC Jamshaid Sarwar Malik, Jameel Nawaz Malik, Ahmed Hemani, Nasirud Din Gohar
2011	C	`conf`	Low-Latency and Low-Overhead Mesochronous and Plesiochronous Synchronizers. DSD Jean-Michel Chabloz, Ahmed Hemani
2011	Misc	`conf`	NoC Based Distributed Partitionable Memory System for a Coarse Grain Reconfigurable Architecture. VLSI Design Muhammad Adeel Tajammul, Muhammad Ali Shami, Ahmed Hemani, Sridharan Moorthi
2011	C	`conf`	Optimal Selection of Function Implementation in a Hierarchical Configware Synthesis Method for a Coarse Grain Reconfigurable Architecture. DSD Fahimeh Jafari, Shuo Li, Ahmed Hemani
2011	A	`conf`	Predicting bus contention effects on energy and performance in multi-processor SoCs. DATE Sandro Penolazzi, Ingo Sander, Ahmed Hemani
2011	—	`conf`	Synchronizing distributed state machines in a coarse grain reconfigurable architecture. SoC Omer Malik, Ahmed Hemani
2010	—	`conf`	A Coarse Grain Reconfigurable Architecture for sequence alignment problems in bio-informatics. SASP Pei Liu, Ahmed Hemani
2010	C	`conf`	Control Scheme for a CGRA. SBAC-PAD Muhammad Ali Shami, Ahmed Hemani
2010	A	`conf`	Distributed DVFS using rationally-related frequencies and discrete voltage levels. ISLPED Jean-Michel Chabloz, Ahmed Hemani
2010	—	`conf`	Improving performance of fading channel simulators by use of uniformly distributed random numbers. ISSPIT Jamshaid Sarwar Malik, Ben Slimane, Ahmed Hemani, Nasirud Din Gohar
2010	—	`conf`	Inferring Energy and Performance Cost of RTOS in Priority-Driven Scheduling. SIES Sandro Penolazzi, Ingo Sander, Ahmed Hemani
2010	C	`conf`	Lowering the latency of interfaces for rationally-related frequencies. ICCD Jean-Michel Chabloz, Ahmed Hemani
2010	—	`conf`	Mapping Optimisation for Scalable Multi-core ARchiTecture: The MOSART Approach. ISVLSI Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch, Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrjä, Fragkiskos Ieromnimon, Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, Philippe Martin
2010	A	`conf`	Predicting energy and performance overhead of Real-Time Operating Systems. DATE Sandro Penolazzi, Ingo Sander, Ahmed Hemani
2010	—	`conf`	The MOSART Mapping Optimization for Multi-Core ARchiTectures. ISVLSI (Selected papers) Bernard Candaele, Sylvain Aguirre, Michel Sarlotte, Iraklis Anagnostopoulos, Sotirios Xydis, Alexandros Bartzas, Dimitris Bekiaris, Dimitrios Soudris, Zhonghai Lu, Xiaowen Chen, Jean-Michel Chabloz, Ahmed Hemani, Axel Jantsch, Geert Vanmeerbeeck, Jari Kreku, Kari Tiensyrjä, Fragkiskos Ieromnimon, Dimitrios Kritharidis, Andreas Wiefrink, Bart Vanthournout, Philippe Martin
2009	Misc	`conf`	A General Approach to High-Level Energy and Performance Estimation in SoCs. VLSI Design Sandro Penolazzi, Ahmed Hemani, Luca Bolognino
2009	J	`jnl`	A General Approach to High-Level Energy and Performance Estimation in System-on-Chip Architectures. J. Low Power Electron. Sandro Penolazzi, Ahmed Hemani, Luca Bolognino
2009	C	`conf`	A flexible communication scheme for rationally-related clock frequencies. ICCD Jean-Michel Chabloz, Ahmed Hemani
2009	C	`conf`	Adaptability infrastructure for bridging IT security evaluation and options theory. SIN Haider Abbas, Louise Yngström, Ahmed Hemani
2009	C	`conf`	Energy and Performance Model of a SPARC Leon3 Processor. DSD Sandro Penolazzi, Luca Bolognino, Ahmed Hemani
2009	—	`conf`	Morphable DPU: Smart and efficient data path for signal processing applications. SiPS Muhammad Ali Shami, Ahmed Hemani
2009	—	`conf`	Option Based Evaluation: Security Evaluation of IT Products Based on Options Theory. ECBS-EERC Haider Abbas, Louise Yngström, Ahmed Hemani
2002	—	`conf`	A Network on Chip Architecture and Design Methodology. ISVLSI Shashi Kumar, Axel Jantsch, Mikael Millberg, Johnny Öberg, Juha-Pekka Soininen, Martti Forsell, Kari Tiensyrjä, Ahmed Hemani
2002	J	`jnl`	Dynamic memory management methodology applied to embedded telecom network systems. IEEE Trans. Very Large Scale Integr. Syst. Chantal Ykman-Couvreur, Jurgen Lambrecht, Diederik Verkest, Francky Catthoor, Bengt Svantesson, Ahmed Hemani, F. Wolf
2001	J	`jnl`	Grammar-based design of embedded systems. J. Syst. Archit. Johnny Öberg, Mattias O'Nils, Axel Jantsch, Adam Postula, Ahmed Hemani
2001	Misc	`conf`	Hardware Software Codesign of DSP System Using Grammar Based Approach. VLSI Design Abhijit K. Deb, Ahmed Hemani, Johnny Öberg, Adam Postula, Dan Lindqvist
2001	J	`jnl`	System-level data-format exploration for dynamically allocated datastructures. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Peeter Ellervee, Miguel Miranda, Francky Catthoor, Ahmed Hemani
2001	C	`conf`	Test Strategies on Functionally Partitioned Module-Based Programmable Architecture for Base-Band Processing. DSD Simon Leung, Adam Postula, Ahmed Hemani
2000	J	`jnl`	A Metamodel for Studying Concepts in Electronic System Design. IEEE Des. Test Comput. Axel Jantsch, Shashi Kumar, Ahmed Hemani
2000	—	`conf`	Development of Programmable Architecture for Base-Band Processing. EUROMICRO Simon Leung, Adam Postula, Ahmed Hemani
2000	J	`jnl`	Grammar-based hardware synthesis from port-size independent specifications. IEEE Trans. Very Large Scale Integr. Syst. Johnny Öberg, Anshul Kumar, Ahmed Hemani
2000	Misc	`conf`	Reconfigurable Architecture for Base-band Data Processing. PDPTA Simon Leung, Adam Postula, Ahmed Hemani
2000	J	`jnl`	System Level Virtual Prototyping of DSP SOCs Using Grammar Based Approach. Des. Autom. Embed. Syst. Ahmed Hemani, Abhijit K. Deb, Johnny Öberg, Adam Postula, Dan Lindqvist, Björn Fjellborg
2000	A*	`conf`	System-level data format exploration for dynamically allocated data structures. DAC Peeter Ellervee, Miguel Miranda, Francky Catthoor, Ahmed Hemani
1999	—	`conf`	Exploiting Data Transfer Locality in Memory Mapping. EUROMICRO Peeter Ellervee, Ahmed Hemani, Miguel Miranda, Francky Catthoor
1999	—	`conf`	Globally asynchronous locally synchronous architecture for large high-performance ASICs. ISCAS (2) Thomas Meincke, Ahmed Hemani, Shashi Kumar, Peeter Ellervee, Johnny Öberg, Thomas Olsson, Peter Nilsson, Dan Lindqvist, Hannu Tenhunen
1999	A*	`conf`	Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style. DAC Ahmed Hemani, Thomas Meincke, Shashi Kumar, Adam Postula, Thomas Olsson, Peter Nilsson, Johnny Öberg, Peeter Ellervee, Dan Lundqvist
1999	C	`conf`	System Level Virtual Prototyping of DSP ASICs Using Grammar Based Approach. IEEE International Workshop on Rapid System Prototyping Ahmed Hemani, Johnny Öberg, Abhijit K. Deb, Dan Lindqvist, Björn Fjellborg
1999	A	`conf`	The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic Systems. DATE Axel Jantsch, Shashi Kumar, Ahmed Hemani
1998	Misc	`conf`	A Methodology and Algorithms for Efficient Interprocess Communication Synthesis from System Description in SDL. VLSI Design Bengt Svantesson, Shashi Kumar, Ahmed Hemani
1998	A	`conf`	Scheduling of Outputs in Grammar-based Hardware Synthesis of Data Communication Protocols. DATE Johnny Öberg, Ahmed Hemani, Anshul Kumar
1998	—	`conf`	Specification of Exception Handling in Grammar-Based Hardware Synthesis. EUROMICRO Johnny Öberg, Anshul Kumar, Ahmed Hemani
1997	—	`conf`	System oriented VLSI curriculum at KTH. MSE Lars Hellberg, Ahmed Hemani, Jouni Isoaho, Axel Jantsch, Mehran Mokhtari, Hannu Tenhunen
1996	Misc	`conf`	A Novell Allocation Strategy for Control and Memory Intensive Telecommunication Circiuts. VLSI Design Bengt Svantesson, Ahmed Hemani, Peeter Ellervee, Adam Postula, Johnny Öberg, Axel Jantsch, Hannu Tenhunen
1996	Misc	`conf`	A Rule-Based Approach for Improving Allocation of Filter Structures in HLS. VLSI Design Johnny Öberg, Jouni Isoaho, Peeter Ellervee, Axel Jantsch, Ahmed Hemani
1996	B	`conf`	Flexible Codesign Target Architecture for Early Prototyping of CMIST Systems. FPL Kalle Tammemäe, Mattias O'Nils, Ahmed Hemani
1996	—	`conf`	Grammar-Based Hardware Synthesis of Data Communication Protocols. ISSS Johnny Öberg, Anshul Kumar, Ahmed Hemani
1994	Misc	`conf`	Application of High-Level Synthesis in an Industrial Project. VLSI Design Ahmed Hemani, Börje Karlsson, Mats Fredriksson, Kurt Nordqvist, Björn Fjellborg
1994	—	`conf`	Hardware/software partitioning and minimizing memory interface traffic. EURO-DAC Axel Jantsch, Peeter Ellervee, Ahmed Hemani, Johnny Öberg, Hannu Tenhunen
1993	Misc	`conf`	Self-Organization and its Application to Binding. VLSI Design Ahmed Hemani
1990	—	`conf`	A neural net based self organising scheduling algorithm. EURO-DAC Ahmed Hemani, Adam Postula
1990	J	`jnl`	Cell placement by self-organisation. Neural Networks Ahmed Hemani, Adam Postula