Ahmad A. Hiasat

29 papers C 2Journal 24Unranked 3

Year	Rank	Type	Title / Venue / Authors
2022	J	`jnl`	An arithmetic scaler circuit design for the expanded four-moduli set {2k-1, 2k+1, 22k+1, 22k}. Comput. Electr. Eng. Ahmad A. Hiasat
2020	J	`jnl`	A Scaler Design for the RNS Three-Moduli Set {2n+1-1, 2n, 2n-1} Based on Mixed-Radix Conversion. J. Circuits Syst. Comput. Ahmad A. Hiasat
2019	J	`jnl`	A Residue-to-Binary Converter with an Adjustable Structure for an Extended RNS Three-Moduli Set. J. Circuits Syst. Comput. Ahmad A. Hiasat
2019	J	`jnl`	On the Design of RNS Inter-Modulo Processing Units for the Arithmetic-Friendly Moduli Sets {2n+k, 2n - 1, 2n+1 - 1}. Comput. J. Ahmad A. Hiasat, Leonel Sousa
2019	J	`jnl`	Sign Identifier for the Enhanced Three Moduli Set {2 n + k , 2 n - 1, 2 n+ 1 - 1}. J. Signal Process. Syst. Ahmad A. Hiasat, Leonel Sousa
2018	J	`jnl`	General modular adder designs for residue number system applications. IET Circuits Devices Syst. Ahmad A. Hiasat
2018	J	`jnl`	New Residue Number System Scaler for the Three-Moduli Set {2 Comput. Ahmad A. Hiasat
2018	J	`jnl`	Sign detector for the extended four-moduli set { 2 IET Comput. Digit. Tech. Ahmad A. Hiasat
2017	J	`jnl`	A Residue-to-Binary Converter for the Extended Four-Moduli Set {2 IEEE Trans. Very Large Scale Integr. Syst. Ahmad A. Hiasat
2017	J	`jnl`	A Reverse Converter and Sign Detectors for an Extended RNS Five-Moduli Set. IEEE Trans. Circuits Syst. I Regul. Pap. Ahmad A. Hiasat
2017	J	`jnl`	An Efficient Reverse Converter for the Three-Moduli Set ( $ 2^{n+1}-1, 2^{n}, 2^{n}-1$ ). IEEE Trans. Circuits Syst. II Express Briefs Ahmad A. Hiasat
2017	J	`jnl`	Efficient RNS Scalers for the Extended Three-Moduli Set (2 IEEE Trans. Computers Ahmad A. Hiasat
2016	J	`jnl`	A Sign Detector for a Group of Three-Moduli Sets. IEEE Trans. Computers Ahmad A. Hiasat
2005	J	`jnl`	VLSI implementation of new arithmetic residue to binary decoders. IEEE Trans. Very Large Scale Integr. Syst. Ahmad A. Hiasat
2004	J	`jnl`	A Suggestion for a Fast Residue Multiplier for a Family of Moduli of the Form (2 Comput. J. Ahmad A. Hiasat
2004	J	`jnl`	A Suggestion for a New RNS-Based Multiplier for a Family of Moduli. Int. J. Comput. Their Appl. Ahmad A. Hiasat
2004	J	`jnl`	Limiter discriminator detection of narrow-band duobinary FSK in a land mobile channel. Int. J. Commun. Syst. Omar Hasan, Ahmad A. Hiasat
2003	J	`jnl`	An arithmetic residue to binary conversion technique. Integr. Ahmad A. Hiasat
2003	J	`jnl`	Bit-serial architecture for rank order and stack filters. Integr. Ahmad A. Hiasat, Omar Hasan
2003	J	`jnl`	Residue number system to binary converter for the moduli set (2 J. Syst. Archit. Ahmad A. Hiasat, Andraos Sweidan
2002	J	`jnl`	High-Speed and Reduced-Area Modular Adder Structures for RNS. IEEE Trans. Computers Ahmad A. Hiasat
2001	J	`jnl`	On the Theory of Error Control Based on Moduli with Common Factors. Reliab. Comput. Andraos Sweidan, Ahmad A. Hiasat
2001	—	`conf`	Semi-custom VLSI chip implementation of a new two-dimensional separable median filtering algorithm. ICECS Ahmad A. Hiasat
2000	J	`jnl`	New Efficient Structure for a Modular Multiplier for RNS. IEEE Trans. Computers Ahmad A. Hiasat
1999	—	`conf`	Full-custom VLSI design of a new high-speed modular adder structures. ICECS Ahmad A. Hiasat
1999	J	`jnl`	Semi-Custom VLSI Design and Implementation of a New Efficient RNS Division Algorithm. Comput. J. Ahmad A. Hiasat, Hoda S. Abdel-Aty-Zohdy
1997	C	`conf`	Design and Implementation of An RNS Division Algorithmm. IEEE Symposium on Computer Arithmetic Ahmad A. Hiasat, Hoda S. Abdel-Aty-Zohdy
1996	—	`conf`	Semi-custom VLSI design for RNS multipliers using combinational logic approach. ICECS Ahmad A. Hiasat
1995	C	`conf`	High-Speed Division Algorithm for Residue Number System. ISCAS Ahmad A. Hiasat, Hoda S. Abdel-Aty-Zohdy