Adrià Armejach

51 papers A* 5A 7B 8C 5Misc 1Journal 18Unranked 6

Year	Rank	Type	Title / Venue / Authors
2026	A	`conf`	Ember: A Compiler for Embedding Operations on Decoupled Access-Execute Architectures. CGO Marco Siracusa, Olivia Hsu, Víctor Soria Pardos, Joshua Randall, Arnaud Grasset, Eric Biscondi, Douglas J. Joseph, Randy Allen, Fredrik Kjolstad, Miquel Moretó Planas, Adrià Armejach
2025	J	`jnl`	A Flexible Instruction Set Architecture for Efficient GEMMs. CoRR Alexandre de Limas Santana, Adrià Armejach, Francesc Martínez, Erich Focht, Marc Casas
2025	A*	`conf`	A. Delegato: Locality-Aware Atomic Memory Operations on Chiplets. MICRO Víctor Soria Pardos, Adrià Armejach, Tiago Mück, Darío Suárez Gracia, José A. Joao, Miquel Moretó
2025	J	`jnl`	Ember: A Compiler for Efficient Embedding Operations on Decoupled Access-Execute Architectures. CoRR Marco Siracusa, Olivia Hsu, Víctor Soria Pardos, Joshua Randall, Arnaud Grasset, Eric Biscondi, Douglas J. Joseph, Randy Allen, Fredrik Kjolstad, Miquel Moretó Planas, Adrià Armejach
2025	C	`conf`	FLAMA: Architecting Floating-Point Atomic Memory Operations for Heterogeneous HPC Systems. DSD Víctor Soria Pardos, Adrià Armejach, Darío Suárez Gracia, Didier Martinot, Arnaud Grasset, Miquel Moretó
2025	J	`jnl`	On Usage of Non-Volatile Memory as Primary Storage for Database Management Systems. CoRR Naveed Ul Mustafa, Adrià Armejach, Ozcan Ozturk, Adrián Cristal, Osman S. Unsal
2025	B	`conf`	Squire: A General-Purpose Accelerator to Exploit Fine-Grain Parallelism on Dependency-Bound Kernels. PACT Rubén Langarita, Jesús Alastruey-Benedé, Pablo Ibáñez-Marín, Santiago Marco-Sola, Miquel Moretó, Adrià Armejach
2025	J	`jnl`	Squire: A General-Purpose Accelerator to Exploit Fine-Grain Parallelism on Dependency-Bound Kernels. CoRR Rubén Langarita, Jesús Alastruey-Benedé, Pablo Ibáñez-Marín, Santiago Marco-Sola, Miquel Moretó, Adrià Armejach
2024	A*	`conf`	A Mess of Memory System Benchmarking, Simulation and Application Profiling. MICRO Pouya Esmaili-Dokht, Francesco Sgherzi, Valéria Soldera Girelli, Isaac Boixaderas, Mariana Carmin, Alireza Monemi, Adrià Armejach, Estanislao Mercadal, Germán Llort, Petar Radojkovic, Miquel Moretó, Judit Giménez, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Emanuele Confalonieri, Rishabh Dubey, Jason Adlard
2024	J	`jnl`	A Mess of Memory System Benchmarking, Simulation and Application Profiling. CoRR Pouya Esmaili-Dokht, Francesco Sgherzi, Valéria Soldera Girelli, Isaac Boixaderas, Mariana Carmin, Alireza Momeni, Adrià Armejach, Estanislao Mercadal, Germán Llort, Petar Radojkovic, Miquel Moretó, Judit Giménez, Xavier Martorell, Eduard Ayguadé, Jesús Labarta, Emanuele Confalonieri, Rishabh Dubey, Jason Adlard
2024	A	`conf`	Exploiting Vector Code Semantics for Efficient Data Cache Prefetching. ICS Francesc Martínez Palau, Martí Torrents, Adrià Armejach, Marc Casas
2024	J	`jnl`	GenArchBench: A genomics benchmark suite for arm HPC processors. Future Gener. Comput. Syst. Lorién López-Villellas, Rubén Langarita-Benítez, Asaf Badouh, Víctor Soria Pardos, Quim Aguado-Puig, Guillem López-Paradís, Max Doblas, Javier Setoain, Chulho Kim, Makoto Ono, Adrià Armejach, Santiago Marco-Sola, Jesús Alastruey-Benedé, Pablo Ibáñez, Miquel Moretó
2024	J	`jnl`	SpChar: Characterizing the sparse puzzle via decision trees. J. Parallel Distributed Comput. Francesco Sgherzi, Marco Siracusa, Ivan Fernandez, Adrià Armejach, Miquel Moretó
2023	A*	`conf`	A Tensor Marshaling Unit for Sparse Tensor Algebra on General-Purpose Processors. MICRO Marco Siracusa, Víctor Soria Pardos, Francesco Sgherzi, Joshua Randall, Douglas J. Joseph, Miquel Moretó Planas, Adrià Armejach
2023	—	`conf`	Characterization of a Coherent Hardware Accelerator Framework for SoCs. SAMOS Guillem López-Paradís, Balaji Venu, Adrià Armejach, Miquel Moretó
2023	A*	`conf`	DynAMO: Improving Parallelism Through Dynamic Placement of Atomic Memory Operations. ISCA Víctor Soria Pardos, Adrià Armejach, Tiago Mück, Darío Suárez Gracia, José A. Joao, Alejandro Rico, Miquel Moretó
2023	B	`conf`	Efficient Direct Convolution Using Long SIMD Instructions. PPoPP Alexandre de Limas Santana, Adrià Armejach, Marc Casas
2023	A	`conf`	Fast Behavioural RTL Simulation of 10B Transistor SoC Designs with Metro-Mpi. DATE Guillem López-Paradís, Brian Li, Adrià Armejach, Stefan Wallentowitz, Miquel Moretó, Jonathan Balkind
2023	J	`jnl`	Porting and Optimizing BWA-MEM2 Using the Fujitsu A64FX Processor. IEEE ACM Trans. Comput. Biol. Bioinform. Rubén Langarita, Adrià Armejach, Pablo Ibáñez, Jesús Alastruey-Benedé, Miquel Moretó
2023	J	`jnl`	SpChar: Characterizing the Sparse Puzzle via Decision Trees. CoRR Francesco Sgherzi, Marco Siracusa, Ivan Fernandez, Adrià Armejach, Miquel Moretó
2022	C	`conf`	A BF16 FMA is All You Need for DNN Training. ARITH John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas
2022	J	`jnl`	A BF16 FMA is All You Need for DNN Training. IEEE Trans. Emerg. Top. Comput. John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas
2022	J	`jnl`	Compressed Sparse FM-Index: Fast Sequence Alignment Using Large K-Steps. IEEE ACM Trans. Comput. Biol. Bioinform. Rubén Langarita, Adrià Armejach, Javier Setoain, Pablo Ibáñez-Marín, Jesús Alastruey-Benedé, Miquel Moretó
2022	B	`conf`	FASE: A Fast, Accurate and Seamless Emulator for Custom Numerical Formats. ISPASS John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas
2022	—	`conf`	FASE: A Fast, Accurate and Seamless Emulator for Custom Numerical Formats. ECML/PKDD (5) John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas
2021	C	`conf`	Dynamically Adapting Floating-Point Precision to Accelerate Deep Neural Network Training. ICMLA John Osorio Ríos, Adrià Armejach, Eric Petit, Greg Henry, Marc Casas
2021	A	`conf`	Mont-Blanc 2020: Towards Scalable and Power Efficient European HPC Processors. DATE Adrià Armejach, Bine Brank, Jordi Cortina, François Dolique, Timothy Hayes, Nam Ho, Pierre-Axel Lagadec, Romain Lemaire, Guillem López-Paradís, Laurent Marliac, Miquel Moretó, Pedro Marcuello, Dirk Pleiter, Xubin Tan, Said Derradji
2021	—	`conf`	Multilevel simulation-based co-design of next generation HPC microprocessors. PMBS Lilia Zaourar, Mohamed Benazouz, Ayoub Mouhagir, Fatma Jebali, Tanguy Sassolas, Jean-Christophe Weill, Carlos Falquez, Nam Ho, Dirk Pleiter, Antoni Portero, Estela Suarez, Polydoros Petrakis, Vassilis Papaefstathiou, Manolis Marazakis, Milan Radulovic, Francesc Martínez, Adrià Armejach, Marc Casas, Alejandro Nocua, Romain Dolbeau
2021	J	`jnl`	On the use of many-core Marvell ThunderX2 processor for HPC workloads. J. Supercomput. Víctor Soria Pardos, Adrià Armejach, Darío Suárez Gracia, Miquel Moretó
2021	A	`conf`	PLANAR: a programmable accelerator for near-memory data rearrangement. ICS Adrián Barredo, Adrià Armejach, Jonathan C. Beard, Miquel Moretó
2021	B	`conf`	gem5 + rtl: A Framework to Enable RTL Models Inside a Full-System Simulator. ICPP Guillem López-Paradís, Adrià Armejach, Miquel Moretó
2020	C	`conf`	Evaluating Mixed-Precision Arithmetic for 3D Generative Adversarial Networks to Simulate High Energy Physics Detectors. ICMLA John Osorio Ríos, Adrià Armejach, Gulrukh Khattak, Eric Petit, Sofia Vallecorsa, Marc Casas
2020	J	`jnl`	The gem5 Simulator: Version 20.0+. CoRR Jason Lowe-Power, Abdul Mutaal Ahmad, Ayaz Akram, Mohammad Alian, Rico Amslinger, Matteo Andreozzi, Adrià Armejach, Nils Asmussen, Srikant Bharadwaj, Gabe Black, Gedare Bloom, Bobby R. Bruce, Daniel Rodrigues Carvalho, Jerónimo Castrillón, Lizhong Chen, Nicolas Derumigny, Stephan Diestelhorst, Wendy Elsasser, Marjan Fariborz, Amin Farmahini Farahani, Pouya Fotouhi, Ryan Gambord, Jayneel Gandhi, Dibakar Gope, Thomas Grass, Bagus Hanindhito, Andreas Hansson, Swapnil Haria, Austin Harris, Timothy Hayes, Adrian Herrera, Matthew Horsnell, Syed Ali Raza Jafri, Radhika Jagtap, Hanhwi Jang, Reiley Jeyapaul, Timothy M. Jones, Matthias Jung, Subash Kannoth, Hamidreza Khaleghzadeh, Yuetsu Kodama, Tushar Krishna, Tommaso Marinelli, Christian Menard, Andrea Mondelli, Tiago Mück, Omar Naji, Krishnendra Nathella, Hoa Nguyen, Nikos Nikoleris, Lena E. Olson, Marc S. Orr, Binh Pham, Pablo Prieto, Trivikram Reddy, Alec Roelke, Mahyar Samani, Andreas Sandberg, Javier Setoain, Boris Shingarov, Matthew D. Sinclair, Tuan Ta, Rahul Thakur, Giacomo Travaglini, Michael Upton, Nilay Vaish, Ilias Vougioukas, Zhengrong Wang, Norbert Wehn, Christian Weis, David A. Wood, Hongil Yoon, Éder F. Zulian
2020	J	`jnl`	Using Arm's scalable vector extension on stencil codes. J. Supercomput. Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rubén Langarita, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó
2019	A	`conf`	Design Space Exploration of Next-Generation HPC Machines. IPDPS Constantino Gómez, Francesc Martínez, Adrià Armejach, Miquel Moretó, Filippo Mantovani, Marc Casas
2019	J	`jnl`	Design trade-offs for emerging HPC processors based on mobile market technology. J. Supercomput. Adrià Armejach, Marc Casas, Miquel Moretó
2018	B	`conf`	Stencil codes on a vector length agnostic architecture. PACT Adrià Armejach, Helena Caminal, Juan M. Cebrian, Rekai González-Alberquilla, Chris Adeniyi-Jones, Mateo Valero, Marc Casas, Miquel Moretó
2016	J	`jnl`	Hardware Acceleration for Query Processing: Leveraging FPGAs, CPUs, and Memory. Comput. Sci. Eng. Oriol Arcas-Abella, Adrià Armejach, Timothy Hayes, Gorker Alp Malazgirt, Oscar Palomar, Behzad Salami, Nehir Sönmez
2016	—	`conf`	Implications of non-volatile memory as primary storage for database management systems. SAMOS Naveed Ul Mustafa, Adrià Armejach, Özcan Özturk, Adrián Cristal, Osman S. Unsal
2016	A	`conf`	MUSA: a multi-level simulation approach for next-generation HPC machines. SC Thomas Grass, César Allande, Adrià Armejach, Alejandro Rico, Eduard Ayguadé, Jesús Labarta, Mateo Valero, Marc Casas, Miquel Moretó
2015	C	`conf`	Tidy Cache: Improving Data Placement in Die-Stacked DRAM Caches. SBAC-PAD Adrià Armejach, Adrián Cristal, Osman S. Unsal
2014	B	`conf`	An empirical evaluation of High-Level Synthesis languages and tools for database acceleration. FPL Oriol Arcas-Abella, Geoffrey Ndu, Nehir Sönmez, Mohsen Ghasempour, Adrià Armejach, Javier Navaridas, Wei Song, John Mawer, Adrián Cristal, Mikel Luján
2014	—	`—`	Techniques to improve concurrency in hardware transactional memory. Adrià Armejach
2013	Misc	`conf`	HARP: Adaptive abort recurrence prediction for Hardware Transactional Memory. HiPC Adrià Armejach, Anurag Negi, Adrián Cristal, Osman S. Unsal, Per Stenström, Tim Harris
2013	J	`jnl`	Techniques to improve performance in requester-wins hardware transactional memory. ACM Trans. Archit. Code Optim. Adrià Armejach, J. Rubén Titos Gil, Anurag Negi, Osman S. Unsal, Adrián Cristal
2012	J	`jnl`	Circuit design of a dual-versioning L1 data cache. Integr. Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero
2012	—	`conf`	Novel SRAM bias control circuits for a low power L1 data cache. NORCHIP Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Mateo Valero
2012	B	`conf`	Transactional prefetching: narrowing the window of contention in hardware transactional memory. PACT Anurag Negi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Per Stenström
2011	—	`conf`	Circuit design of a dual-versioning L1 data cache for optimistic concurrency. ACM Great Lakes Symposium on VLSI Azam Seyedi, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Ibrahim Hur, Mateo Valero
2011	B	`conf`	Using a Reconfigurable L1 Data Cache for Efficient Version Management in Hardware Transactional Memory. PACT Adrià Armejach, Azam Seyedi, J. Rubén Titos Gil, Ibrahim Hur, Adrián Cristal, Osman S. Unsal, Mateo Valero
2009	A*	`conf`	EazyHTM: eager-lazy hardware transactional memory. MICRO Sasa Tomic, Cristian Perfumo, Chinmay Eishan Kulkarni, Adrià Armejach, Adrián Cristal, Osman S. Unsal, Tim Harris, Mateo Valero