Adrian Kneip

12 papers C 1Journal 8Unranked 2
YearRankTypeTitle / Venue / Authors
2025 C conf
An Event-Based Digital Compute-In-Memory Accelerator with Flexible Operand Resolution and Layer-Wise Weight/Output Stationarity.
ISCAS
Nicolas Chauvaux, Adrian Kneip, Christoph Posch, Kofi A. A. Makinwa, Charlotte Frenkel
2025 J jnl
EvGNN: An Event-Driven Graph Neural Network Accelerator for Edge Vision.
IEEE Trans. Circuits Syst. Artif. Intell.
Yufeng Yang, Adrian Kneip, Charlotte Frenkel
2025 J jnl
IMAGINE: An 8-to-1b 22nm FD-SOI Compute-In-Memory CNN Accelerator With an End-to-End Analog Charge-Based 0.15-8POPS/W Macro Featuring Distribution-Aware Data Reshaping.
IEEE Trans. Circuits Syst. Artif. Intell.
Adrian Kneip, Martin Lefebvre, Pol Maistriaux, David Bol
2024 J jnl
An Event-Based Digital Compute-In-Memory Accelerator with Flexible Operand Resolution and Layer-Wise Weight/Output Stationarity.
CoRR
Nicolas Chauvaux, Adrian Kneip, Christoph Posch, Kofi A. A. Makinwa, Charlotte Frenkel
2024 — —
Bridging the hardware-software co-design gap in analog compute-in-memory accelerators towards edge CNN classification.
Adrian Kneip
2024 J jnl
EvGNN: An Event-driven Graph Neural Network Accelerator for Edge Vision.
CoRR
Yufeng Yang, Adrian Kneip, Charlotte Frenkel
2024 J jnl
IMAGINE: An 8-to-1b 22nm FD-SOI Compute-In-Memory CNN Accelerator With an End-to-End Analog Charge-Based 0.15-8POPS/W Macro Featuring Distribution-Aware Data Reshaping.
CoRR
Adrian Kneip, Martin Lefebvre, Pol Maistriaux, David Bol
2023 J jnl
A 7T-NDR Dual-Supply 28-nm FD-SOI Ultra-Low Power SRAM With 0.23-nW/kB Sleep Retention and 0.8 pJ/32b Access at 64 MHz With Forward Back Bias.
IEEE Trans. Circuits Syst. I Regul. Pap.
Adrian Kneip, David Bol
2023 J jnl
IMPACT: A 1-to-4b 813-TOPS/W 22-nm FD-SOI Compute-in-Memory CNN Accelerator Featuring a 4.2-POPS/W 146-TOPS/mm
IEEE J. Solid State Circuits
Adrian Kneip, Martin Lefebvre, Julien Verecken, David Bol
2022 — conf
A 1-to-4b 16.8-POPS/W 473-TOPS/mm2 6T-based In-Memory Computing SRAM in 22nm FD-SOI with Multi-Bit Analog Batch-Normalization.
ESSCIRC
Adrian Kneip, Martin Lefebvre, Julien Verecken, David Bol
2021 J jnl
Impact of Analog Non-Idealities on the Design Space of 6T-SRAM Current-Domain Dot-Product Operators for In-Memory Computing.
IEEE Trans. Circuits Syst. I Regul. Pap.
Adrian Kneip, David Bol
2021 — conf
SleepRider: a 5.5μW/MHz Cortex-M4 MCU in 28nm FD-SOI with ULP SRAM, Biomedical AFE and Fully-Integrated Power, Clock and Back-Bias Management.
VLSI Circuits
Rémi Dekimpe, Maxime Schramme, Martin Lefebvre, Adrian Kneip, Roghayeh Saeidi, Mathieu Xhonneux, Ludovic Moreau, Marco Gonzalez, Thibault Pirson, David Bol