Aditya Japa

19 papers A* 1C 4Misc 1Journal 8Unranked 5
YearRankTypeTitle / Venue / Authors
2025 J jnl
FeSATLock: An Energy Efficient and SAT Attack Resilient Logic Locking Design With FeFET LUT Architecture for Enhanced Hardware Security.
IEEE Access
Tirumalarao Kadiyam, Venu Birudu, Aditya Japa, Fadi N. Sibai, Venkateswarlu Gonuguntla, Ramesh Vaddi
2025 A* conf
Security of Approximate Neural Networks against Power Side-channel Attacks.
DAC
Aditya Japa, Jack Miskelly, Máire O'Neill, Chongyan Gu
2025 Misc conf
Special Sessions - Emerging Scope and Design Challenges for Approximate Computing: Optimizing Accuracy-PPA trade-offs and Beyond.
CASES
Siva Satyendra Sahoo, Bastien Deveautour, Marcello Traiola, Chongyan Gu, Yun Wu, Aditya Japa, Salim Ullah, Akash Kumar
2024 C conf
A Novel Methodology for Processor based PUF in Approximate Computing.
ISCAS
Aditya Japa, Jack Miskelly, Yijun Cui, Máire O'Neill, Chongyan Gu
2024 C conf
Negative Capacitance FET 8T SRAM Computing in-Memory based Logic Design for Energy Efficient AI Edge Devices.
ISCAS
Venu Birudu, Tirumalarao Kadiyam, Koteswararao Penumalli, Aditya Japa, Sushma Nirmala Sambatur, Chongyan Gu, Siva Sankar Yellampalli, Ramesh Vaddi
2023 J jnl
Negative capacitance FET based energy efficient and DPA attack resilient ultra-light weight block cipher design.
Microelectron. J.
Renuka Chowdary Bheemana, Aditya Japa, Siva Sankar Yellampalli, Ramesh Vaddi
2023 — conf
Processor based Intrinsic PUF Design for Approximate Computing: Faith or Reality?
AsianHOST
Aditya Japa, Jiliang Zhang, Weiqiang Liu, Chongyan Gu
2022 — conf
A Reconfigurable Arbiter PUF Based on VGSOT MTJ.
VDAT
Kunal Kranti Das, Aditya Japa, Deepika Gupta
2022 J jnl
Negative capacitance FETs for energy efficient and hardware secure logic designs.
Microelectron. J.
Renuka Chowdary Bheemana, Aditya Japa, Siva Sankar Yellampalli, Ramesh Vaddi
2021 — conf
Steep Switching NCFET based Logic for Future Energy Efficient Electronics.
iSES
Renuka Chowdary Bheemana, Aditya Japa, Siva Sankar Yellampalli, Ramesh Vaddi
2021 J jnl
Tunnel FET-based ultra-lightweight reconfigurable TRNG and PUF design for resource-constrained internet of things.
Int. J. Circuit Theory Appl.
Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
2020 C conf
A Low Voltage Discriminant Circuit for Pattern Recognition Exploiting the Asymmetrical Characteristics of Tunnel FET.
ISCAS
Aditya Japa, Yellappa Palagani, Venkateswarlu Gonuguntla, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Jun Rim Choi, Ramesh Vaddi
2020 J jnl
Low area overhead DPA countermeasure exploiting tunnel transistor-based random number generator.
IET Circuits Devices Syst.
Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
2020 J jnl
Tunnel FET-based ultralow-power and hardware-secure circuit design considering p-i-n forward leakage.
Int. J. Circuit Theory Appl.
Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
2019 J jnl
Tunnel FET ambipolarity-based energy efficient and robust true random number generator against reverse engineering attacks.
IET Circuits Devices Syst.
Aditya Japa, Manoj Kumar Majumder, Subhendu Kumar Sahoo, Ramesh Vaddi
2018 C conf
Tunneling Field Effect Transistors for Enhancing Energy Efficiency and Hardware Security of IoT Platforms: Challenges and Opportunities.
ISCAS
Aditya Japa, T. Nagateja, Santosh Kumar Vishvakarma, Yellappa Palagani, Jun Rim Choi, Ramesh Vaddi
2017 — conf
Exploiting Characteristics of Steep Slope Tunnel Transistors Towards Energy Efficient and Reliable Buffer Designs for IoT SoCs.
VDAT
Aditya Japa, Harshita Vallabhaneni, Ramesh Vaddi
2017 — conf
Tunneling Field Effect Transistors for Energy Efficient Logic, Sensor Interface and 3D IC Circuits for IoT Platforms.
iNIS
Aditya Japa, T. Nagateja, Ramesh Vaddi
2016 J jnl
Reliability enhancement of a steep slope tunnel transistor based ring oscillator designs with circuit interaction.
IET Circuits Devices Syst.
Aditya Japa, Harshita Vallabhaneni, Ramesh Vaddi