Aditya Bansal - RankMe

29 papers A* 2A 4B 1C 1Misc 2Journal 9Unranked 9

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	Human-LLM Collaborative Feature Engineering for Tabular Data. CoRR Zhuoyan Li, Aditya Bansal, Jinzhao Li, Shishuang He, Zhuoran Lu, Mutian Zhang, Qin Liu, Yiwei Yang, Swati Jain, Ming Yin, Yunyao Li
2025	J	`jnl`	Navigating the Reality Gap: Privacy-Preserving On-Device Continual Adaptation of ASR for Clinical Telephony. CoRR Darshil Chauhan, Adityasinh Solanki, Vansh Patel, Kanav Kapoor, Ritvik Jain, Aditya Bansal, Pratik Narang, Dhruv Kumar
2024	B	`conf`	Compressing VAE-Based Out-of-Distribution Detectors for Embedded Deployment. RTCSA Aditya Bansal, Michael Yuhas, Arvind Easwaran
2024	J	`jnl`	Compressing VAE-Based Out-of-Distribution Detectors for Embedded Deployment. CoRR Aditya Bansal, Michael Yuhas, Arvind Easwaran
2024	—	`conf`	MMBCD: Multimodal Breast Cancer Detection from Mammograms with Clinical History. MICCAI (1) Kshitiz Jain, Aditya Bansal, Krithika Rangarajan, Chetan Arora
2021	J	`jnl`	Whether the weather will help us weather the COVID-19 pandemic: Using machine learning to measure twitter users' perceptions. Int. J. Medical Informatics Marichi Gupta, Aditya Bansal, Bhav Jain, Jillian Rochelle, Atharv Oak, Mohammad S. Jalali
2016	—	`conf`	Covariance computation in MHE: A nonlinear regression approach. ICCA Aditya Bansal, Mani Bhushan, Lorenz T. Biegler
2014	J	`jnl`	Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module. IEEE J. Solid State Circuits James D. Warnock, Yuen H. Chan, Hubert Harrer, Sean M. Carey, Gerard Salem, Doug Malone, Ruchir Puri, Jeffrey A. Zitz, Adam Jatkowski, Gerald Strevig, Ayan Datta, Anne Gattiker, Aditya Bansal, Guenter Mayer, Yiu-Hing Chan, Mark D. Mayo, David L. Rude, Leon J. Sigal, Thomas Strach, Howard H. Smith, Huajun Wen, Pak-kin Mak, Chung-Lung Kevin Shum, Donald W. Plass, Charles F. Webb
2013	—	`conf`	5.5GHz system z microprocessor and multi-chip module. ISSCC James D. Warnock, Yuen H. Chan, Hubert Harrer, David L. Rude, Ruchir Puri, Sean M. Carey, Gerard Salem, Guenter Mayer, Yiu-Hing Chan, Mark D. Mayo, Adam Jatkowski, Gerald Strevig, Leon J. Sigal, Ayan Datta, Anne Gattiker, Aditya Bansal, Doug Malone, Thomas Strach, Huajun Wen, Pak-kin Mak, Chung-Lung Kevin Shum, Donald W. Plass, Charles F. Webb
2012	—	`conf`	DRC-free high density layout exploration with layout morphing and patterning quality assessment, with application to SRAM. ISQED Amith Singhee, Emrah Acar, Mohammad Imran Younus, Rama N. Singh, Aditya Bansal
2011	—	`ch.`	Variations: Sources and Characterization. Low-Power Variation-Tolerant Design in Nanometer Silicon Aditya Bansal, Rahul M. Rao
2009	J	`jnl`	Impacts of NBTI and PBTI on SRAM static/dynamic noise margins and cell failure probability. Microelectron. Reliab. Aditya Bansal, Rahul M. Rao, Jae-Joon Kim, Sufi Zafar, James H. Stathis, Ching-Te Chuang
2009	A	`conf`	Yield estimation of SRAM circuits using "Virtual SRAM Fab". ICCAD Aditya Bansal, Rama N. Singh, Rouwaida Kanj, Saibal Mukhopadhyay, Jin-Fuw Lee, Emrah Acar, Amith Singhee, Keunwoo Kim, Ching-Te Chuang, Sani R. Nassif, Fook-Luen Heng, Koushik K. Das
2008	J	`jnl`	An alternate design paradigm for low-power, low-cost, testable hybrid systems using scaled LTPS TFTs. ACM J. Emerg. Technol. Comput. Syst. Jing Li, Aditya Bansal, Swaroop Ghosh, Kaushik Roy
2008	Misc	`conf`	Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies. VLSI Design Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy
2008	C	`conf`	Pre-Si estimation and compensation of SRAM layout deficiencies to achieve target performance and yield. ICCD Aditya Bansal, Rama N. Singh, Saibal Mukhopadhyay, Geng Han, Fook-Luen Heng, Ching-Te Chuang
2007	—	`conf`	FinFET SRAM: Optimizing Silicon Fin Thickness and Fin Ratio to Improve Stability at iso Area. CICC Dheepa Lekshmanan, Aditya Bansal, Kaushik Roy
2007	A*	`conf`	High Performance and Low Power Electronics on Flexible Substrate. DAC Jing Li, Kunhyuk Kang, Aditya Bansal, Kaushik Roy
2007	J	`jnl`	Self-Consistent Approach to Leakage Power and Temperature Estimation to Predict Thermal Runaway in FinFET Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy
2006	A*	`conf`	A high density, carbon nanotube capacitor for decoupling applications. DAC Mark M. Budnik, Arijit Raychowdhury, Aditya Bansal, Kaushik Roy
2006	J	`jnl`	An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Aditya Bansal, Bipul Chandra Paul, Kaushik Roy
2006	A	`conf`	Circuit-aware device design methodology for nanometer technologies: a case study for low power SRAM design. DATE Qikai Chen, Saibal Mukhopadhyay, Aditya Bansal, Kaushik Roy
2006	—	`conf`	Compact thermal models for estimation of temperature-dependent power/performance in FinFET technology. ASP-DAC Aditya Bansal, Mesut Meterelliyoz, Siddharth Singh, Jung Hwan Choi, Jayathi Murthy, Kaushik Roy
2006	Misc	`conf`	Double-Gate SOI Devices for Low-Power and High-Performance Applications. VLSI Design Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici
2006	A	`conf`	Leakage power dependent temperature estimation to predict thermal runaway in FinFET circuits. ICCAD Jung Hwan Choi, Aditya Bansal, Mesut Meterelliyoz, Jayathi Murthy, Kaushik Roy
2005	—	`conf`	Asymmetric halo CMOSFET to reduce static power dissipation with improved performance. ISCAS (1) Aditya Bansal, Kaushik Roy
2005	A	`conf`	Double-gate SOI devices for low-power and high-performance applications. ICCAD Kaushik Roy, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Hari Ananthan, Aditya Bansal, Tamer Cakici
2005	—	`conf`	Modeling and optimization approach to robust and low-power FinFET SRAM design in nanoscale era. CICC Aditya Bansal, Saibal Mukhopadhyay, Kairshik Roy
2004	—	`conf`	FinFET SRAM - Device and Circuit Design Considerations. ISQED Hari Ananthan, Aditya Bansal, Kaushik Roy