Adit D. Singh - RankMe

161 papers A* 1A 25B 11C 6Misc 43Journal 34Unranked 40

Year	Rank	Type	Title / Venue / Authors
2025	A	`conf`	Efficient Delay Fault Characterization of Resistive Open Defects in Standard Cells Using Resistive Fault Dominance. ITC Gowsika Dharmaraj, Abhijit Chatterjee, Adit D. Singh, Arani Sinha
2025	A*	`conf`	Invited: Enhancing Test Quality by Targeting Timing Marginalities Due to Process Variations. DAC Adit D. Singh, Mukarram Ali Faridi
2025	Misc	`conf`	Silent Data Corruption: Advancing Detection, Diagnosis, and Mitigation Strategies. VTS Peter Domanski, Mukarram Ali Faridi, Gabriel Kaunang, Wilson Pradeep, Adit D. Singh, Muhammad Alfian Amrizal, Yanjing Li, Farshad Firouzi, Krishnendu Chakrabarty
2024	Misc	`conf`	Innovative Practices Track: Session 2 Silent Data Corruption. VTS Arani Sinha, Adit D. Singh
2024	B	`conf`	Silent Data Corruption from Timing Marginalities Due to Process Variations. ETS Adit D. Singh
2023	Misc	`conf`	Silent Data Errors: Sources, Detection, and Modeling. VTS Adit D. Singh, Sreejit Chakravarty, George Papadimitriou, Dimitris Gizopoulos
2023	—	`conf`	Silent Error Corruption: The New Reliability and Test Challenge. LATS Adit D. Singh
2022	J	`jnl`	A Systematic Bit Selection Method for Robust SRAM PUFs. J. Electron. Test. Wendong Wang, Adit D. Singh, Ujjwal Guin
2022	A	`conf`	Understanding Vmin Failures for Improved Testing of Timing Marginalities. ITC Adit D. Singh
2021	J	`jnl`	Estimating Operational Age of an Integrated Circuit. J. Electron. Test. Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal
2021	J	`jnl`	Exploring the Mysteries of System-Level Test. CoRR Ilia Polian, Jens Anders, Steffen Becker, Paolo Bernardi, Krishnendu Chakrabarty, Nourhan Elhamawy, Matthias Sauer, Adit D. Singh, Matteo Sonza Reorda, Stefan Wagner
2021	J	`jnl`	High Resolution Pulse Propagation Driven Trojan Detection in Digital Systems. J. Electron. Test. Sabyasachi Deyati, Barry J. Muldrey, Adit D. Singh, Abhijit Chatterjee
2021	Misc	`conf`	Two Pattern Timing Tests Capturing Defect-Induced Multi-Gate Delay Impact of Shorts. VTS Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee
2020	Misc	`conf`	A Zero-Cost Detection Approach for Recycled ICs using Scan Architecture. VTS Wendong Wang, Ujjwal Guin, Adit D. Singh
2020	J	`jnl`	Aging-Resilient SRAM-based True Random Number Generator for Lightweight Devices. J. Electron. Test. Wendong Wang, Ujjwal Guin, Adit D. Singh
2020	—	`conf`	Exploring the Mysteries of System-Level Test. ATS Ilia Polian, Jens Anders, Steffen Becker, Paolo Bernardi, Krishnendu Chakrabarty, Nourhan Elhamawy, Matthias Sauer, Adit D. Singh, Matteo Sonza Reorda, Stefan Wagner
2020	A	`conf`	SAT-ATPG Generated Multi-Pattern Scan Tests for Cell Internal Defects: Coverage Analysis for Resistive Opens and Shorts. ITC Sujay Pandey, Zhiwei Liao, Shreyas Nandi, Sanya Gupta, Suriyaprakash Natarajan, Arani Sinha, Adit D. Singh, Abhijit Chatterjee
2019	A	`conf`	An Adaptive Approach to Minimize System Level Tests Targeting Low Voltage DVFS Failures. ITC Adit D. Singh
2019	—	`conf`	Detecting Recycled SoCs by Exploiting Aging Induced Biases in Memory Cells. HOST Ujjwal Guin, Wendong Wang, Charles Harper, Adit D. Singh
2019	Misc	`conf`	Two-Pattern ∆IDDQ Test for Recycled IC Detection. VLSID Prattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal
2018	Misc	`conf`	A Secure Low-Cost Edge Device Authentication Scheme for the Internet of Things. VLSID Ujjwal Guin, Adit D. Singh, Mahabubul Alam, Janice Canedo, Anthony Skjellum
2018	B	`conf`	Device aging: A reliability and security concern. ETS Daniel Kraak, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Francky Catthoor, Abhijit Chatterjee, Adit D. Singh, Hans-Joachim Wunderlich, Naghmeh Karimi
2018	—	`conf`	Exploiting power supply ramp rate for calibrating cell strength in SRAM PUFs. LATS Wendong Wang, Adit D. Singh, Ujjwal Guin, Abhijit Chatterjee
2018	J	`jnl`	On the Generation of Waveform-Accurate Hazard and Charge-Sharing Aware Tests for Transistor Stuck-Off Faults in CMOS Logic Circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Jan Burchard, Dominik Erb, Sudhakar M. Reddy, Adit D. Singh, Bernd Becker
2018	J	`jnl`	Robust Design-for-Security Architecture for Enabling Trust in IC Manufacturing and Test. IEEE Trans. Very Large Scale Integr. Syst. Ujjwal Guin, Ziqi Zhou, Adit D. Singh
2017	J	`jnl`	A Reliability-Aware Methodology to Isolate Timing-Critical Paths under Aging. J. Electron. Test. Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja
2017	Misc	`conf`	A novel design-for-security (DFS) architecture to prevent unauthorized IC overproduction. VTS Ujjwal Guin, Ziqi Zhou, Adit D. Singh
2017	B	`conf`	Best paper. ETS Bernd Becker, Adit D. Singh
2017	Misc	`conf`	Efficient SAT-based generation of hazard-activated TSOF tests. VTS Jan Burchard, Dominik Erb, Sudhakar M. Reddy, Adit D. Singh, Bernd Becker
2017	A	`conf`	Exploiting path delay test generation to develop better TDF tests for small delay defects. ITC Ankush Srivastava, Adit D. Singh, Virendra Singh, Kewal K. Saluja
2017	A	`conf`	Fast and waveform-accurate hazard-aware SAT-based TSOF ATPG. DATE Jan Burchard, Dominik Erb, Adit D. Singh, Sudhakar M. Reddy, Bernd Becker
2017	—	`conf`	Identifying high variability speed-limiting paths under aging. LATS Ankush Srivastava, Virendra Singh, Adit D. Singh, Kewal K. Saluja
2016	Misc	`conf`	Adaptive Test Methods for High IC Quality and Reliability. VLSID Adit D. Singh
2016	B	`conf`	Cell Aware and stuck-open tests. ETS Adit D. Singh
2016	—	`conf`	Noise-Resilient SRAM Physically Unclonable Function Design for Security. ATS Sujay Pandey, Sabyasachi Deyati, Adit D. Singh, Abhijit Chatterjee
2015	—	`conf`	A Methodology for Identifying High Timing Variability Paths in Complex Designs. ATS Virendra Singh, Adit D. Singh, Kewal K. Saluja
2015	Misc	`conf`	An Efficient Transition Detector Exploiting Charge Sharing. VLSID Yu Wang, Adit D. Singh
2015	—	`conf`	Challenge Engineering and Design of Analog Push Pull Amplifier Based Physically Unclonable Function for Hardware Security. ATS Sabyasachi Deyati, Barry John Muldrey, Adit D. Singh, Abhijit Chatterjee
2015	Misc	`conf`	Embedded Tutorial ET1: Better-than-Worst-Case Timing Designs. VLSID Adit D. Singh
2015	—	`conf`	Scan based two-pattern tests: should they target opens instead of TDFs? LATS Adit D. Singh
2015	Misc	`conf`	Special session: Hot topics: Statistical test methods. VTS Manuel J. Barragán, Gildas Léger, Florence Azaïs, Ronald D. Blanton, Adit D. Singh, Stephen Sunter
2015	Misc	`conf`	Testing cross wire opens within complex gates. VTS Chao Han, Adit D. Singh
2014	Misc	`conf`	Better-than-Worst-Case Timing Design with Latch Buffers on Short Paths. VLSID Ravi Kanth Uppu, Ravi Tej Uppu, Adit D. Singh, Ilia Polian
2014	B	`conf`	Detection conditions for errors in self-adaptive better-than-worst-case designs. ETS Ilia Polian, Jie Jiang, Adit D. Singh
2014	B	`conf`	Error detection and recovery in better-than-worst-case timing designs. ETS Adit D. Singh
2014	—	`conf`	High Resolution Pulse Propagation Driven Trojan Detection in Digital Logic: Optimization Algorithms and Infrastructure. ATS Sabyasachi Deyati, Barry John Muldrey, Adit D. Singh, Abhijit Chatterjee
2014	Misc	`conf`	Improving CMOS open defect coverage using hazard activated tests. VTS Chao Han, Adit D. Singh
2014	A	`conf`	On the testing of hazard activated open defects. ITC Chao Han, Adit D. Singh
2014	—	`conf`	Timing Evaluation Tests for Scan Enable Signals with Application to TDF Testing. ATS Jie Zou, Chao Han, Adit D. Singh
2014	Misc	`conf`	Timing Variation Adaptive Pipeline Design: Using Probabilistic Activity Completion Sensing with Backup Error Resilience. VLSID Jayaram Natarajan, Sahil Kapoor, Debesh Bhatta, Abhijit Chatterjee, Adit D. Singh
2013	Misc	`conf`	A High Throughput Multiplier Design Exploiting Input Based Statistical Distribution in Completion Delays. VLSI Design Ravi Tej Uppu, Ravi Kanth Uppu, Adit D. Singh, Abhijit Chatterjee
2013	B	`conf`	Current testing: Dead or alive? ETS Hans A. R. Manhaeve, Pete Harrod, Adit D. Singh, Chintan Patel, Ralf Arnolc, Davide Appello
2013	C	`conf`	Embedded tutorials: Embedded tutorial 1: Cell-aware test-from gates to transistors. VLSI-SoC Janusz Rajski, Miodrag Potkonjak, Adit D. Singh, Abhijit Chatterjee, Zain Navabi, Matthew R. Guthaus, Sezer Gören
2013	—	`conf`	Hazard Initialized LOC Tests for TDF Undetectable CMOS Open Defects. Asian Test Symposium Chao Han, Adit D. Singh
2013	Misc	`conf`	Special session 4B: Elevator talks. VTS Jennifer Dworak, Ronald Shawn Blanton, Masahiro Fujita, Kazumi Hatayama, Naghmeh Karimi, Michail Maniatakos, Antonis M. Paschalis, Adit D. Singh, Tian Xia
2013	—	`ed.`	VLSI Design and Test, 17th International Symposium, VDAT 2013, Jaipur, India, July 27-30, 2013, Revised Selected Papers VDAT Manoj Singh Gaur, Mark Zwolinski, Vijay Laxmi, Dharmendar Boolchandani, Virendra Singh, Adit D. Singh
2012	Misc	`conf`	Detection of gate-oxide defects with timing tests at reduced power supply. VTS Xi Qian, Chao Han, Adit D. Singh
2012	—	`conf`	SEU Tolerant Robust Latch Design. VDAT Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita
2012	C	`conf`	SEU tolerant robust memory cell design. IOLTS Mohammed Shayan, Virendra Singh, Adit D. Singh, Masahiro Fujita
2011	—	`conf`	Diagnosing Multiple Slow Gates for Performance Tuning in the Face of Extreme Process Variations. Asian Test Symposium Xi Qian, Adit D. Singh, Abhijit Chatterjee
2011	—	`conf`	Distributed Comparison Test Driven Multiprocessor Speed-Tuning: Targeting Performance Gains under Extreme Process Variations. Asian Test Symposium Jayaram Natarajan, Joshua W. Wells, Abhijit Chatterjee, Adit D. Singh
2011	Misc	`conf`	Path Delay Tuning for Performance Gain in the Face of Random Manufacturing Variations. VLSI Design Kautalya Mishra, Ahmed Faraz, Adit D. Singh
2011	—	`conf`	SSTKR: Secure and Testable Scan Design through Test Key Randomization. Asian Test Symposium Mohammed Abdul Razzaq, Virendra Singh, Adit D. Singh
2010	A	`conf`	Adapting to adaptive testing. DATE Erik Jan Marinissen, Adit D. Singh, Dan Glotter, Marco Esposito, John M. Carulli Jr., Amit Nahar, Kenneth M. Butler, Davide Appello, Chris Portelli
2010	Misc	`conf`	An output compression scheme for handling X-states from over-clocked delay tests. VTS Adit D. Singh, Chao Han, Xi Qian
2010	—	`conf`	Current Sensing Completion Detection for high speed and area efficient arithmetic. APCCAS Balapradeep Gadamsetti, Adit D. Singh
2010	—	`conf`	Distinguishing Resistive Small Delay Defects from Random Parameter Variations. Asian Test Symposium Xi Qian, Adit D. Singh
2010	—	`conf`	Modified Scan Flip-Flop for Low Power Testing. Asian Test Symposium Amit Mishra, Nidhi Sinha, Satdev, Virendra Singh, Sreejit Chakravarty, Adit D. Singh
2010	B	`conf`	Modified T-Flip-Flop based scan cell for RAS. ETS Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Adit D. Singh
2010	Misc	`conf`	On Minimization of Test Application Time for RAS. VLSI Design Raghavendra Adiga, Gandhi Arpit, Virendra Singh, Kewal K. Saluja, Hideo Fujiwara, Adit D. Singh
2010	J	`jnl`	Post-Manufacture Tuning for Nano-CMOS Yield Recovery Using Reconfigurable Logic. IEEE Trans. Very Large Scale Integr. Syst. Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh
2010	C	`conf`	Test application time minimization for RAS using basis optimization of column decoder. ISCAS A. Abhishek, Amanulla Khan, Virendra Singh, Kewal K. Saluja, Adit D. Singh
2009	—	`conf`	A Defect Tolerant and Performance Tunable Gate Architecture for End-of-Roadmap CMOS. DFT Adit D. Singh
2009	—	`conf`	Leveraging Partially Enhanced Scan for Improved Observability in Delay Fault Testing. Asian Test Symposium K. G. Deepak, Robinson Reyna, Virendra Singh, Adit D. Singh
2009	Misc	`conf`	Output Hazard-Free Transition Delay Fault Test Generation. VTS Sreekumar Menon, Adit D. Singh, Vishwani D. Agrawal
2009	C	`conf`	Panel: Realistic low power design: Let errors occur and correct them later or mitigate errors via design guardbanding and process control?. IOLTS Abhijit Chatterjee, Jacob A. Abraham, Adit D. Singh, Elie Maricau, Rakesh Kumar, Christos A. Papachristou
2008	Misc	`conf`	Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS. VLSI Design Maryam Ashouei, Adit D. Singh, Abhijit Chatterjee
2008	A	`conf`	Scan Based Testing of Dual/Multi Core Processors for Small Delay Defects. ITC Adit D. Singh
2008	Misc	`conf`	Scan Delay Testing of Nanometer SoCs. VLSI Design Adit D. Singh
2007	A	`conf`	Achieving high transition delay fault coverage with partial DTSFF scan chains. ITC Gefu Xu, Adit D. Singh
2007	Misc	`conf`	Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing. VLSI Design Gefu Xu, Adit D. Singh
2007	—	`conf`	Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan. ATS Gefu Xu, Adit D. Singh
2007	Misc	`conf`	Probabilistic Self-Adaptation of Nanoscale CMOS Circuits: Yield Maximization under Increased Intra-Die Variations. VLSI Design Maryam Ashouei, Muhammad Mudassar Nisar, Abhijit Chatterjee, Adit D. Singh, Abdulkadir Utku Diril
2007	J	`jnl`	Scan cell design for launch-on-shift delay tests with slow scan enable. IET Comput. Digit. Tech. Gefu Xu, Adit D. Singh
2006	J	`jnl`	A New Delay Test Based on Delay Defect Detection Within Slack Intervals (DDSI). IEEE Trans. Very Large Scale Integr. Syst. Haihua Yan, Adit D. Singh
2006	J	`jnl`	Analysis and Optimization of Nanometer CMOS Circuits for Soft-Error Tolerance. IEEE Trans. Very Large Scale Integr. Syst. Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
2006	J	`jnl`	Combining Negative Binomial and Weibull Distributions for Yield and Reliability Prediction. IEEE Des. Test Comput. Thomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh
2006	J	`jnl`	Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects. J. Electron. Test. Xiangdong Xuan, Adit D. Singh, Abhijit Chatterjee
2006	B	`conf`	Low Cost Launch-on-Shift Delay Test with Slow Scan Enable. ETS Gefu Xu, Adit D. Singh
2006	J	`jnl`	New JETTA Editors, 2006. J. Electron. Test. Bashir M. Al-Hashimi, Dimitris Gizopoulos, Manoj Sachdev, Adit D. Singh
2006	Misc	`conf`	Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing. VTS Adit D. Singh, Gefu Xu
2006	Misc	`conf`	Statistical Estimation of Correlated Leakage Power Variation and Its Application to Leakage-Aware Design. VLSI Design Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De, T. M. Mak
2005	Misc	`conf`	A Delay Test to Differentiate Resistive Interconnect Faults from Weak Transistor Defects. VLSI Design Haihua Yan, Adit D. Singh
2005	C	`conf`	A Dual-Vt Layout Approach for Statistical Leakage Variability Minimization in Nanometer CMOS. ICCD Maryam Ashouei, Abhijit Chatterjee, Adit D. Singh, Vivek De
2005	A	`conf`	A random access scans architecture to reduce hardware overhead. ITC Anand S. Mudlapur, Vishwani D. Agrawal, Adit D. Singh
2005	A	`conf`	A self-timed structural test methodology for timing anomalies due to defects and process variations. ITC Adit D. Singh
2005	—	`conf`	Delay Defect Characterization Using Low Voltage Test. Asian Test Symposium Haihua Yan, Adit D. Singh, Gefu Xu
2005	Misc	`conf`	Design of Adaptive Nanometer Digital Systems for Effective Control of Soft Error Tolerance. VTS Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
2005	Misc	`conf`	Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages. VLSI Design Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
2005	J	`jnl`	Level-shifter free design of low power dual supply voltage CMOS circuits using dual threshold voltages. IEEE Trans. Very Large Scale Integr. Syst. Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
2005	—	`conf`	Low Voltage Test in Place of Fast Clock in DDSI Delay Test. ISQED Haihua Yan, Gefu Xu, Adit D. Singh
2005	—	`conf`	Low-power domino circuits using NMOS pull-up on off-critical paths. ASP-DAC Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
2005	J	`jnl`	Pseudo Dual Supply Voltage Domino Logic Design. J. Low Power Electron. Abdulkadir Utku Diril, Yuvraj Singh Dhillon, Abhijit Chatterjee, Adit D. Singh
2005	—	`conf`	T2: Statistical Methods for VLSI Test and Burn-in Optimization. Asian Test Symposium Adit D. Singh
2004	B	`conf`	Application of local design-for-reliability techniques for reducing wear-out degradation of CMOS combinational logic circuits. ETS Xiangdong Xuan, Abhijit Chatterjee, Adit D. Singh
2004	A	`conf`	Evaluating the Effectiveness of Detecting Delay Defects in the Slack Interval: A Simulation Study. ITC Haihua Yan, Adit D. Singh
2004	—	`conf`	Low-power dual V SBCCI Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
2004	—	`conf`	Reduce Yield Loss in Delay Defect Detection in Slack Interval. Asian Test Symposium Haihua Yan, Adit D. Singh
2004	C	`conf`	Sizing CMOS Circuits for Increased Transient Error Tolerance. IOLTS Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh
2003	A	`conf`	Experiments in Detecting Delay Faults using Multiple Higher Frequency Clocks and Results from Neighboring Die. ITC Haihua Yan, Adit D. Singh
2003	J	`jnl`	Extending integrated-circuit yield-models to estimate early-life reliability. IEEE Trans. Reliab. Thomas S. Barnett, Adit D. Singh, Victor P. Nelson
2003	—	`conf`	IC Reliability Simulator ARET and Its Application in Design-for-Reliability. Asian Test Symposium Xiangdong Xuan, Abhijit Chatterjee, Adit D. Singh, Namsoo P. Kim, Mark T. Chisa
2003	—	`conf`	Integrating Yield, Test and Reliability: "Statistical Models with Applications to Test and Burn-in Optimization". ISQED Adit D. Singh
2003	J	`jnl`	Multimode scan: Test per clock BIST for IP cores. ACM Trans. Design Autom. Electr. Syst. Adit D. Singh, Markus Seuring, Michael Gössel, Egor S. Sogomonyan
2003	A	`conf`	Relating Yield Models to Burn-In Fall-Out in Time. ITC Thomas S. Barnett, Adit D. Singh
2003	A	`conf`	Should Nanometer Circuits be Periodically Tested in the Field? ITC Adit D. Singh
2002	A	`conf`	Redundancy Implications for Early-Life Reliability: Experimental Verification of an Integrated Yield-Reliability Model. ITC Thomas S. Barnett, Matt Grady, Kathleen G. Purdy, Adit D. Singh
2002	Misc	`conf`	Scan-Path with Directly Duplicated and Inverted Duplicated Registers. VTS Michael Gössel, Egor S. Sogomonyan, Adit D. Singh
2002	Misc	`conf`	Yield-Reliability Modeling: Experimental Verification and Application to Burn-In Reduction. VTS Thomas S. Barnett, Adit D. Singh, Matt Grady, Kathleen G. Purdy
2001	Misc	`conf`	Burn-In Failures and Local Region Yield: An Integrated Yield-Reliability Model. VTS Thomas S. Barnett, Adit D. Singh, Victor P. Nelson
2001	Misc	`conf`	Early Error Detection in Systems-on-Chip for Fault-Tolerance and At-Speed Debugging. VTS Egor S. Sogomonyan, Andrej A. Morosov, Jan Rzeha, Michael Gössel, Adit D. Singh
2001	A	`conf`	Estimating burn-in fall-out for redundant memory. ITC Thomas S. Barnett, Adit D. Singh, Victor P. Nelson
2001	—	`conf`	Yield-Reliability Modeling for Fault Tolerant Integrated Circuits. DFT Thomas S. Barnett, Adit D. Singh, Victor P. Nelson
1999	J	`jnl`	A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing. J. Electron. Test. Egor S. Sogomonyan, Adit D. Singh, Michael Gössel
1999	A	`conf`	Exploiting defect clustering to screen bare die for infant mortality failures: an experimental study. ITC David R. Lakin II, Adit D. Singh
1999	A	`conf`	Testability evaluation of sequential designs incorporating the multi-mode scannable memory element. ITC Adit D. Singh, Egor S. Sogomonyan, Michael Gössel, Markus Seuring
1998	Misc	`conf`	A Multi-Mode Scannable Memory Element for High Test Application Efficiency and Delay Testing. VTS Egor S. Sogomonyan, Adit D. Singh, Michael Gössel
1998	J	`jnl`	An IDDQ sensor for concurrent timing error detection. IEEE J. Solid State Circuits Christopher G. Knight, Adit D. Singh, Victor P. Nelson
1998	—	`conf`	Binning for IC Quality: Experimental Studies on the SEMATECH Data. DFT Adit D. Singh, David R. Lakin II, Gaurav Sinha, Phil Nigh
1997	J	`jnl`	A differential built-in current sensor design for high-speed IDDQ testing. IEEE J. Solid State Circuits Jason P. Hurst, Adit D. Singh
1997	—	`conf`	An IDDQ Sensor for Concurrent Timing Error Detection. DFT Christopher G. Knight, Adit D. Singh, Victor P. Nelson
1997	J	`jnl`	Incorporating J. Electron. Test. Walter W. Weber, Adit D. Singh
1997	A	`conf`	Screening for Known Good Die (KGD) Based on Defect Clustering: An Experimental Study. ITC Adit D. Singh, Phil Nigh, C. Mani Krishna
1996	J	`jnl`	On the Effect of Defect Clustering on Test Transparency and IC Test Optimization. IEEE Trans. Computers Adit D. Singh, C. Mani Krishna
1995	Misc	`conf`	A differential built-in current sensor design for high speed IDDQ testing. VLSI Design Jason P. Hurst, Adit D. Singh
1995	—	`conf`	ADTS: an array defect-tolerance scheme for wafer scale gate arrays. DFT Adit D. Singh
1995	J	`jnl`	Adaptive Unanimous Voting (UV) Scheme for Distributed Self-Diagnosis. IEEE Trans. Computers Jae Young Lee, Hee Yong Youn, Adit D. Singh
1995	Misc	`conf`	An experimental evaluation of the differential BICS for I VTS Walter W. Weber, Adit D. Singh
1995	A	`conf`	I ITC Adit D. Singh, Haroon Rasheed, Walter W. Weber
1994	Misc	`conf`	Incorporating IDDQ testing in BIST: improved coverage through test diversity. VTS Adit D. Singh, Jason P. Hurst
1993	—	`conf`	Adaptive Voting for Faulty (VFF) Node Scheme for Distributed Self-Diagnosis. FTCS Jae Young Lee, Hee Yong Youn, Adit D. Singh
1993	J	`jnl`	On optimizing VLSI testing for product quality using die-yield prediction. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Adit D. Singh, C. Mani Krishna
1993	Misc	`conf`	The effect of defect clustering on test transparency and defect levels. VTS Adit D. Singh, C. Mani Krishna
1992	Misc	`conf`	Analysis of the die test optimization algorithm for negative binomial yield statistics. VTS C. Mani Krishna, Adit D. Singh
1992	—	`conf`	Chip Test Optimization Using Defect Clustering Information. FTCS Adit D. Singh, C. Mani Krishna
1991	J	`jnl`	A Modular Fault-Tolerant Binary Tree Architecture with Short Links. IEEE Trans. Computers Adit D. Singh, Hee Yong Youn
1991	A	`conf`	On Optimizing Wafer-Probe Testing for Product Quality Using Die-Yield Prediction. ITC Adit D. Singh, C. Mani Krishna
1991	J	`jnl`	Yield optimization in large RAM's with hierarchical redundancy. IEEE J. Solid State Circuits Kumar N. Ganapathy, Adit D. Singh, Dhiraj K. Pradhan
1990	J	`jnl`	Fault Tolerance in VLSI Circuits. Computer Israel Koren, Adit D. Singh
1990	J	`jnl`	Fault-Tolerant Systems - Guest Editors' Introduction to the Special Issue. Computer Adit D. Singh, Singaravel Murugesan
1989	—	`conf`	A Near Optimal Adaptive Row Modular Design for Efficiently Reconfiguring the Processor Array in VLSI. ICPP (1) Hee Yong Youn, Adit D. Singh
1989	J	`jnl`	A single cached copy data coherence scheme for multiprocessor systems. SIGARCH Comput. Archit. News Abraham Mendelson, Dhiraj K. Pradhan, Adit D. Singh
1989	A	`conf`	An efficient channel routing algorithm for defective arrays. ICCAD Hee Yong Youn, Adit D. Singh
1989	—	`conf`	Modelling correlated transient failures in fault-tolerant systems. FTCS C. Mani Krishna, Adit D. Singh
1989	J	`jnl`	On Implementing Large Binary Tree Architectures in VLSI and WSI. IEEE Trans. Computers Hee Yong Youn, Adit D. Singh
1988	—	`conf`	A Highly Efficient Design for Reconfiguring the Processor Array in VLSI. ICPP (1) Hee Yong Youn, Adit D. Singh
1988	J	`jnl`	Interstitial Redundancy: An Area Efficient Fault Tolerance Scheme for Large Area VLSI Processor Arrays. IEEE Trans. Computers Adit D. Singh
1988	A	`conf`	Near Optimal Embedding of Binary Tree Architecture in VLSI. ICDCS Hee Yong Youn, Adit D. Singh
1987	B	`conf`	On Area Efficient and Fault Tolerant Tree Embedding In VLSI. ICPP Hee Yong Youn, Adit D. Singh
1981	J	`jnl`	Tree Structured Sequential Multiple-Valued Logic Design from Universal Modules. IEEE Trans. Computers Adit D. Singh, F. Gail Gray, James R. Armstrong
1978	—	`conf`	A simultaneous, radix four, I2L multiplier mechanized via repeated addition. MVL Adit D. Singh, James R. Armstrong