Adib Nahiyan

16 papers A* 2A 1Misc 2Journal 9Unranked 2
YearRankTypeTitle / Venue / Authors
2021 J jnl
Security Assessment of Dynamically Obfuscated Scan Chain Against Oracle-guided Attacks.
ACM Trans. Design Autom. Electr. Syst.
M. Sazadur Rahman, Adib Nahiyan, Fahim Rahman, Saverio Fazzari, Kenneth Plaks, Farimah Farahmandi, Domenic Forte, Mark Tehranipoor
2020 J jnl
A Physical Design Flow Against Front-Side Probing Attacks by Internal Shielding.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Huanyu Wang, Qihang Shi, Adib Nahiyan, Domenic Forte, Mark Tehranipoor
2020 J jnl
SCRIPT: A CAD Framework for Power Side-channel Vulnerability Assessment Using Information Flow Tracking and Pattern Generation.
ACM Trans. Design Autom. Electr. Syst.
Adib Nahiyan, Jungmin Park, Miao Tony He, Yousef Iskander, Farimah Farahmandi, Domenic Forte, Mark Tehranipoor
2020 Misc conf
SeRFI: Secure Remote FPGA Initialization in an Untrusted Environment.
VTS
Adam Duncan, Adib Nahiyan, Fahim Rahman, Grant Skipper, Martin Swany, Andrew Lukefahr, Farimah Farahmandi, Mark Tehranipoor
2020 J jnl
Soft-HaT: Software-Based Silicon Reprogramming for Hardware Trojan Implementation.
ACM Trans. Design Autom. Electr. Syst.
Md. Mahbub Alam, Adib Nahiyan, Mehdi Sadi, Domenic Forte, Mark Tehranipoor
2019 J jnl
Dynamically Obfuscated Scan Chain To Resist Oracle-Guided Attacks On Logic Locked Design.
IACR Cryptol. ePrint Arch.
M. Sazadur Rahman, Adib Nahiyan, Sarah Amir, Fahim Rahman, Farimah Farahmandi, Domenic Forte, Mark Tehranipoor
2019 — conf
FLATS: Filling Logic and Testing Spatially for FPGA Authentication and Tamper Detection.
HOST
Adam Duncan, Grant Skipper, Andrew Stern, Adib Nahiyan, Fahim Rahman, Andrew Lukefahr, Mark Tehranipoor, Martin Swany
2019 Misc conf
RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level.
VTS
Miao Tony He, Jungmin Park, Adib Nahiyan, Apostol Vassilev, Yier Jin, Mark Tehranipoor
2019 J jnl
RTL-PSC: Automated Power Side-Channel Leakage Assessment at Register-Transfer Level.
CoRR
Miao Tony He, Jungmin Park, Adib Nahiyan, Apostol Vassilev, Yier Jin, Mark Tehranipoor
2019 J jnl
Security-Aware FSM Design Flow for Identifying and Mitigating Vulnerabilities to Fault Attacks.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
Adib Nahiyan, Farimah Farahmandi, Prabhat Mishra, Domenic Forte, Mark Tehranipoor
2018 J jnl
Hardware Trojan Detection through Information Flow Security Verification.
CoRR
Adib Nahiyan, Mehdi Sadi, Rahul Vittal, Gustavo K. Contreras, Domenic Forte, Mark Tehranipoor
2017 A conf
Hardware trojan detection through information flow security verification.
ITC
Adib Nahiyan, Mehdi Sadi, Rahul Vittal, Gustavo K. Contreras, Domenic Forte, Mark Tehranipoor
2017 — conf
Security vulnerability analysis of design-for-test exploits for asset protection in SoCs.
ASP-DAC
Gustavo K. Contreras, Adib Nahiyan, Swarup Bhunia, Domenic Forte, Mark Tehranipoor
2017 A* conf
Standardizing Bad Cryptographic Practice: A Teardown of the IEEE Standard for Protecting Electronic-design Intellectual Property.
CCS
Animesh Chhotaray, Adib Nahiyan, Thomas Shrimpton, Domenic Forte, Mark Tehranipoor
2016 A* conf
AVFSM: a framework for identifying and mitigating vulnerabilities in FSMs.
DAC
Adib Nahiyan, Kan Xiao, Kun Yang, Yier Jin, Domenic Forte, Mark Tehranipoor
2016 J jnl
Security Rule Checking in IC Design.
Computer
Kan Xiao, Adib Nahiyan, Mark Tehranipoor