Adam Teman - RankMe

98 papers A* 2A 4C 20Journal 54Unranked 18

Year	Rank	Type	Title / Venue / Authors
2026	J	`jnl`	GainP: A Gain Cell Embedded DRAM-based associative in-memory processor. J. Syst. Archit. Yaniv Levi, Odem Harel, Adam Teman, Leonid Yavits
2026	J	`jnl`	GenMClass: Design and comparative analysis of genome classifier-on-chip platform. J. Syst. Archit. Daria Bromot, Yehuda Kra, Zuher Jahshan, Esteban Garzón, Adam Teman, Leonid Yavits
2026	J	`jnl`	PiC-BNN: A 128-kbit 65 nm Processing-in-CAM-Based End-to-End Binary Neural Network Accelerator. CoRR Yuval Harary, Almog Sharoni, Esteban Garzón, Marco Lanuzza, Adam Teman, Leonid Yavits
2026	J	`jnl`	SPADE: A SIMD Posit-enabled compute engine for Accelerating DNN Efficiency. CoRR Sonu Kumar, Lavanya Vinnakota, Mukul Lokhande, Santosh Kumar Vishvakarma, Adam Teman
2026	J	`jnl`	SPARCAM: Sparse matrix multiplication accelerator using multi-port dynamic CAM. J. Syst. Archit. Esteban Garzón, Benjamin Zambrano, David Sheinenzon, Marco Lanuzza, Adam Teman, Leonid Yavits
2025	J	`jnl`	A 128-kbit Approximate Search-Capable Content-Addressable Memory (CAM) With Tunable Hamming Distance. IEEE J. Solid State Circuits Esteban Garzón, Eyal Rechef, Roman Golman, Odem Harel, Yuval Harary, Paz Snapir, Marco Lanuzza, Adam Teman, Leonid Yavits
2025	J	`jnl`	A 16-kB 65-nm GC-eDRAM Macro With Internal Bias Voltage Generation Providing Over 100-μs Retention Time. IEEE J. Solid State Circuits Odem Harel, Halil Andaç Yigit, Eliana Feifel, Robert Giterman, Andreas Burg, Adam Teman
2025	J	`jnl`	Bhasha-Rupantarika: Algorithm-Hardware Co-design approach for Multilingual Neural Machine Translation. CoRR Mukul Lokhande, Tanushree Dewangan, Mohd Sharik Mansoori, Tejas Chaudhari, Akarsh J., Damayanti Lokhande, Adam Teman, Santosh Kumar Vishvakarma
2025	J	`jnl`	CORDIC Is All You Need. CoRR Omkar Kokane, Adam Teman, Anushka Jha, Guru Prasath SL, Gopal Raut, Mukul Lokhande, S. V. Jaya Chand, Tanushree Dewangan, Santosh Kumar Vishvakarma
2025	—	`conf`	KSPiM: A 65nm Processing-near-Memory State-Space Accelerator for Keyword Spotting. CCMCC Almog Sharoni, Zuher Jahshan, Yehuda Kra, Adam Teman, Leonid Yavits
2025	C	`conf`	LPRE: Logarithmic Posit-enabled Reconfigurable edge-AI Engine. ISCAS Omkar Kokane, Mukul Lokhande, Gopal Raut, Adam Teman, Santosh Kumar Vishvakarma
2025	—	`conf`	PiC-BNN: A 128-kbit 65 nm Processing-in-CAM-Based End-to-End Binary Neural Network Accelerator. CCMCC Yuval Harary, Almog Sharoni, Esteban Garzón, Marco Lanuzza, Adam Teman, Leonid Yavits
2025	—	`conf`	Retrospective: A CORDIC Based Configurable Activation Function for NN Applications. ISVLSI Omkar Kokane, Gopal Raut, Salim Ullah, Mukul Lokhande, Adam Teman, Akash Kumar, Santosh Kumar Vishvakarma
2025	J	`jnl`	Retrospective: A CORDIC Based Configurable Activation Function for NN Applications. CoRR Omkar Kokane, Gopal Raut, Salim Ullah, Mukul Lokhande, Adam Teman, Akash Kumar, Santosh Kumar Vishvakarma
2025	C	`conf`	Towards Low-Power High-Performance Content-Addressable Memory: A Robust Precharge-Free Approach. ISCAS Ramiro Taco, Esteban Garzón, Adam Teman, Leonid Yavits, Marco Lanuzza
2024	—	`conf`	A 4T GC-eDRAM Bitcell with Differential Readout Mechanism For High Performance Applications. PRIME Roman Golman, Avinoam Segev, Adam Teman
2024	—	`conf`	Basecalling by Statistical Profiling and Hardware-Accelerated Convolutional Neural Network. PRIME Yehuda Kra, Yehuda Rudin, Alexander Fish, Adam Teman
2024	J	`jnl`	Designing Precharge-Free Energy-Efficient Content-Addressable Memories. IEEE Trans. Very Large Scale Integr. Syst. Ramiro Taco, Esteban Garzón, Robert Hanhan, Adam Teman, Leonid Yavits, Marco Lanuzza
2024	J	`jnl`	FASTA: Revisiting Fully Associative Memories in Computer Microarchitecture. IEEE Access Esteban Garzón, Robert Hanhan, Marco Lanuzza, Adam Teman, Leonid Yavits
2024	J	`jnl`	HAMSA-DI: A Low-Power Dual-Issue RISC-V Core Targeting Energy-Efficient Embedded Systems. IEEE Trans. Circuits Syst. I Regul. Pap. Yehuda Kra, Yonatan Shoshan, Yehuda Rudin, Adam Teman
2024	—	`conf`	Methodologies for Device Characterization in Cryogenic Temperatures. PRIME Noam Roknian, Yonatan Shoshan, Inbal Stanger, Menachem Goldzweig, Yoav Weizmann, Adam Teman, Edoardo Charbon, Alexander Fish
2024	J	`jnl`	Revisiting Dynamic Logic - A True Candidate for Energy-Efficient Cryogenic Operation in Nanoscaled Technologies. IEEE Trans. Circuits Syst. I Regul. Pap. Inbal Stanger, Noam Roknian, Netanel Shavit, Yonatan Shoshan, Yoav Weizman, Adam Teman, Edoardo Charbon, Alexander Fish
2024	A	`conf`	Selfie5: An Autonomous, Self-Contained Verification Approach for High-Throughput Random Testing of Programmable Processors. DATE Yehuda Kra, Naama Kra, Adam Teman
2023	J	`jnl`	A Low-Complexity Sensing Scheme for Approximate Matching Content-Addressable Memory. IEEE Trans. Circuits Syst. II Express Briefs Esteban Garzón, Roman Golman, Marco Lanuzza, Adam Teman, Leonid Yavits
2023	J	`jnl`	A Low-Energy DMTJ-Based Ternary Content- Addressable Memory With Reliable Sub-Nanosecond Search Operation. IEEE Access Esteban Garzón, Leonid Yavits, Giovanni Finocchio, Mario Carpentieri, Adam Teman, Marco Lanuzza
2023	J	`jnl`	AM IEEE J. Emerg. Sel. Topics Circuits Syst. Esteban Garzón, Marco Lanuzza, Adam Teman, Leonid Yavits
2023	J	`jnl`	Efficient Implementation of Many-Ported Memories by Using Standard-Cell Memory Approach. IEEE Access Hanan Marinberg, Esteban Garzón, Tzachi Noy, Marco Lanuzza, Adam Teman
2023	—	`conf`	Overview of Cryogenic Operation in Nanoscale Technology Nodes. LASCAS Noam Roknian, Yonatan Shoshan, Inbal Stanger, Adam Teman, Edoardo Charbon, Alexander Fish
2023	—	`conf`	STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications. LASCAS Esteban Garzón, Leonid Yavits, Adam Teman, Marco Lanuzza
2022	C	`conf`	A RISC-V-based Research Platform for Rapid Design Cycle. ISCAS Esteban Garzón, Roman Golman, Odem Harel, Tzachi Noy, Yehuda Kra, Asaf Pollock, Slava Yuzhaninov, Yonatan Shoshan, Yehuda Rudin, Yoav Weizman, Marco Lanuzza, Adam Teman
2022	J	`jnl`	AIDA: Associative In-Memory Deep Learning Accelerator. IEEE Micro Esteban Garzón, Adam Teman, Marco Lanuzza, Leonid Yavits
2022	J	`jnl`	Adjusting Thermal Stability in Double-Barrier MTJ for Energy Improvement in Cryogenic STT-MRAMs. CoRR Esteban Garzón, Raffaele De Rose, Felice Crupi, Lionel Trojman, Adam Teman, Marco Lanuzza
2022	A*	`conf`	EDAM: edit distance tolerant approximate matching content addressable memory. ISCA Robert Hanhan, Esteban Garzón, Zuher Jahshan, Adam Teman, Marco Lanuzza, Leonid Yavits
2022	C	`conf`	Evaluation of Dual Mode Logic Under Cryogenic Temperatures. ISCAS Inbal Stanger, Noam Roknian, Yonatan Shoshan, Zafrir Levy, Yoav Weizman, Edoardo Charbon, Adam Teman, Alexander Fish
2022	J	`jnl`	Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for DNA Classification. IEEE Access Esteban Garzón, Roman Golman, Zuher Jahshan, Robert Hanhan, Natan Vinshtok-Melnik, Marco Lanuzza, Adam Teman, Leonid Yavits
2022	—	`conf`	SerOpt: Transistor Sizing Algorithm and Optimization Utility for Minimizing Soft Error Rate. DCIS Yehuda Kra, Yoav Weizman, Adam Teman
2022	C	`conf`	Silicon-Proven Clockless Wave-Propagated Pipelining for High-Throughput, Energy-Efficient Processing. ISCAS Yehuda Kra, Adam Teman
2021	C	`conf`	4T Gain-Cell Providing Unlimited Availability through Hidden Refresh with 1W1R Functionality. ISCAS Einat Levy, Aharon Sfez, Roman Golman, Odem Harel, Adam Teman
2021	J	`jnl`	Gain-Cell Embedded DRAM Under Cryogenic Operation - A First Study. IEEE Trans. Very Large Scale Integr. Syst. Esteban Garzón, Yosi Greenblatt, Odem Harel, Marco Lanuzza, Adam Teman
2021	J	`jnl`	Hamming Distance Tolerant Content-Addressable Memory (HD-CAM) for Approximate Matching Applications. CoRR Esteban Garzón, Roman Golman, Zuher Jahshan, Robert Hanhan, Natan Vinshtok-Melnik, Marco Lanuzza, Adam Teman, Leonid Yavits
2021	J	`jnl`	Refresh Algorithm for Ensuring 100% Memory Availability in Gain-Cell Embedded DRAM Macros. IEEE Access Roman Golman, Netanel Nachum, Tomer Cohen, Robert Giterman, Adam Teman
2021	A	`conf`	WP 2.0: Signoff-Quality Implementation and Validation of Energy-Efficient Clock-Less Wave Propagated Pipelining. DATE Yehuda Kra, Tzachi Noy, Adam Teman
2020	J	`jnl`	Current-Based Data-Retention-Time Characterization of Gain-Cell Embedded DRAMs Across the Design and Variations Space. IEEE Trans. Circuits Syst. I Fundam. Theory Appl. Robert Giterman, Andrea Bonetti, Ester Vicario Bravo, Tzachi Noy, Adam Teman, Andreas Burg
2020	J	`jnl`	Design of a Refresh-Controller for GC-eDRAM Based FIFOs. IEEE Trans. Circuits Syst. Tzachi Noy, Adam Teman
2020	C	`conf`	GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI. ISCAS Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman
2020	C	`conf`	Gain-Cell Embedded DRAMs: Modeling and Design Space. ISCAS Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg
2020	J	`jnl`	Gain-Cell Embedded DRAMs: Modeling and Design Space. IEEE Trans. Very Large Scale Integr. Syst. Andrea Bonetti, Roman Golman, Robert Giterman, Adam Teman, Andreas Burg
2020	C	`conf`	Improved Read Access in GC-eDRAM Memory by Dual-Negative Word-Line Technique. ISCAS Roman Golman, Robert Giterman, Odem Harel, Adam Teman
2020	J	`jnl`	Physically Aware Affinity-Driven Multiplier Implementation. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. Or Maltabashi, Yehuda Kra, Adam Teman
2020	A	`conf`	WavePro: Clock-less Wave-Propagated Pipeline Compiler for Low-Power and High-Throughput Computation. DATE Yehuda Kra, Tzachi Noy, Adam Teman
2019	J	`jnl`	GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI. IEEE Trans. Circuits Syst. II Express Briefs Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman
2019	J	`jnl`	Improving Energy-Efficiency in Dynamic Memories Through Retention Failure Detection. IEEE Access Robert Giterman, Roman Golman, Adam Teman
2019	—	`conf`	TEMPO: Thermal-Efficient Management of Power in High-Throughput Network Switches. VLSI-DAT Tom Munk, Hillel Kugler, Ofir Maori, Adam Teman
2018	J	`jnl`	A 4-Transistor nMOS-Only Logic-Compatible Gain-Cell Embedded DRAM With Over 1.6-ms Retention Time at 700 mV in 28-nm FD-SOI. IEEE Trans. Circuits Syst. I Regul. Pap. Robert Giterman, Alexander Fish, Andreas Burg, Adam Teman
2018	C	`conf`	A 5-Transistor Ternary Gain-Cell eDRAM with Parallel Sensing. ISCAS Or Maltabashi, Hanan Marinberg, Robert Giterman, Adam Teman
2018	J	`jnl`	A 588-Gb/s LDPC Decoder Based on Finite-Alphabet Message Passing. IEEE Trans. Very Large Scale Integr. Syst. Reza Ghanaatian, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Michael Meidlinger, Gerald Matz, Adam Teman, Andreas Burg
2018	J	`jnl`	An 800-MHz Mixed- V IEEE J. Solid State Circuits Robert Giterman, Alexander Fish, Narkis Geuli, Elad Mentovich, Andreas Burg, Adam Teman
2018	—	`conf`	Configurable Multi-Port Dynamic Bitcell with Internal Refresh Mechanism. ICECS Roman Golman, Robert Giterman, Adam Teman
2018	J	`jnl`	Gain-Cell Embedded DRAM-Based Physical Unclonable Function. IEEE Trans. Circuits Syst. I Regul. Pap. Robert Giterman, Yoav Weizman, Adam Teman
2018	—	`conf`	High Density GC-eDRAM Design in 16nm FinFET. ICECS Amir Shalom, Robert Giterman, Adam Teman
2018	C	`conf`	Live Demonstration: An 800 Mhz Gain-Cell Embedded DRAM in 28 nm CMOS Bulk Process for Approximate Computing Applications. ISCAS Robert Giterman, Roman Golman, Amir Shalom, Or Maltabashi, Alexander Fish, Adam Teman
2017	J	`jnl`	A 0.65-V, 500-MHz Integrated Dynamic and Static RAM for Error Tolerant Applications. IEEE Trans. Very Large Scale Integr. Syst. Amit Kazimirsky, Adam Teman, Noa Edri, Alexander Fish
2017	J	`jnl`	A 594 Gbps LDPC Decoder Based on Finite-Alphabet Message Passing. CoRR Reza Ghanaatian, Alexios Balatsoukas-Stimming, Thomas Christoph Müller, Michael Meidlinger, Gerald Matz, Adam Teman, Andreas Burg
2017	—	`conf`	An 800 Mhz mixed-VT 4T gain-cell embedded DRAM in 28 nm CMOS bulk process for approximate computing applications. ESSCIRC Robert Giterman, Alexander Fish, Narkis Geuli, Elad Mentovich, Andreas Burg, Adam Teman
2017	J	`jnl`	Area and Energy-Efficient Complementary Dual-Modular Redundancy Dynamic Memory for Space Applications. IEEE Trans. Very Large Scale Integr. Syst. Robert Giterman, Lior Atias, Adam Teman
2017	J	`jnl`	Automated Integration of Dual-Edge Clocking for Low-Power Operation in Nanometer Nodes. ACM Trans. Design Autom. Electr. Syst. Andrea Bonetti, Nicholas Preyss, Adam Teman, Andreas Burg
2017	J	`jnl`	Energy-Efficient Near-Threshold Parallel Computing: The PULPv2 Cluster. IEEE Micro Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Philippe Flatresse, Luca Benini
2017	J	`jnl`	Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation. IEEE Trans. Circuits Syst. II Express Briefs Robert Giterman, Adam Teman, Pascal Meinerzhagen
2017	J	`jnl`	Multipliers-Driven Perturbation of Coefficients for Low-Power Operation in Reconfigurable FIR Filters. IEEE Trans. Circuits Syst. I Regul. Pap. Andrea Bonetti, Adam Teman, Philippe Flatresse, Andreas Burg
2016	—	`conf`	193 MOPS/mW @ 162 MOPS, 0.32V to 1.15V voltage range multi-core accelerator for energy efficient parallel and sequential digital processing. COOL Chips Davide Rossi, Antonio Pullini, Igor Loi, Michael Gautschi, Frank Kagan Gürkaynak, Adam Teman, Jeremy Constantin, Andreas Burg, Ivan Miro Panades, Edith Beigné, Fabien Clermidy, Fady Abouzeid, Philippe Flatresse, Luca Benini
2016	J	`jnl`	A Low-Voltage Radiation-Hardened 13T SRAM Bitcell for Ultralow Power Space Applications. IEEE Trans. Very Large Scale Integr. Syst. Lior Atias, Adam Teman, Robert Giterman, Pascal Meinerzhagen, Alexander Fish
2016	C	`conf`	A low-power correlator for wakeup receivers with algorithm pruning through early termination. ISCAS Reza Ghanaatian, Paul N. Whatmough, Jeremy Constantin, Adam Teman, Andreas Burg
2016	C	`conf`	A process compensated gain cell embedded-DRAM for ultra-low-power variation-aware design. ISCAS Robert Giterman, Adam Teman, Pascal Meinerzhagen, Alexander Fish, Andreas Burg
2016	—	`conf`	DynOR: A 32-bit microprocessor in 28 nm FD-SOI with cycle-by-cycle dynamic clock adjustment. ESSCIRC Jeremy Constantin, Andrea Bonetti, Adam Teman, Thomas Christoph Müller, Lorenz Schmid, Andreas Burg
2016	J	`jnl`	Power, Area, and Performance Optimization of Standard Cell Memory Arrays Through Controlled Placement. ACM Trans. Design Autom. Electr. Syst. Adam Teman, Davide Rossi, Pascal Meinerzhagen, Luca Benini, Andreas Burg
2016	J	`jnl`	Silicon-Proven, Per-Cell Retention Time Distribution Model for Gain-Cell Based eDRAMs. IEEE Trans. Circuits Syst. I Regul. Pap. Noa Edri, Pascal Meinerzhagen, Adam Teman, Andreas Burg, Alexander Fish
2016	J	`jnl`	Single-Supply 3T Gain-Cell for Low-Voltage Low-Power Applications. IEEE Trans. Very Large Scale Integr. Syst. Robert Giterman, Adam Teman, Pascal Andreas Meinerzhagen, Lior Atias, Andreas Burg, Alexander Fish
2016	J	`jnl`	Synthesis of Dual Mode Logic. Integr. Lior Moyal, Itamar Levi, Adam Teman, Alexander Fish
2015	J	`jnl`	A Fast Modular Method for True Variation-Aware Separatrix Tracing in Nanoscaled SRAMs. IEEE Trans. Very Large Scale Integr. Syst. Adam Teman, Roman Visotsky
2015	C	`conf`	An overlap-contention free true-single-phase clock dual-edge-triggered flip-flop. ISCAS Andrea Bonetti, Adam Teman, Andreas Burg
2015	—	`conf`	Approximate computing with unreliable dynamic memories. NEWCAS Shrikanth Ganapathy, Adam Teman, Robert Giterman, Andreas Burg, Georgios Karakonstantis
2015	—	`conf`	Controlled placement of standard cell memory arrays for high density and low power in 28nm FD-SOI. ASP-DAC Adam Teman, Davide Rossi, Pascal Andreas Meinerzhagen, Luca Benini, Andreas Peter Burg
2015	A	`conf`	Energy versus data integrity trade-offs in embedded high-density logic compatible dynamic memories. DATE Adam Teman, Georgios Karakonstantis, Robert Giterman, Pascal Andreas Meinerzhagen, Andreas Peter Burg
2015	A*	`conf`	Mitigating the impact of faults in unreliable memories for error-resilient applications. DAC Shrikanth Ganapathy, Georgios Karakonstantis, Adam Teman, Andreas Burg
2014	C	`conf`	4T Gain-Cell with internal-feedback for ultra-low retention power at scaled CMOS nodes. ISCAS Robert Giterman, Adam Teman, Pascal Andreas Meinerzhagen, Andreas Burg, Alexander Fish
2014	J	`jnl`	A Low-Power Low-Cost 24 GHz RFID Tag With a C-Flash Based Embedded Memory. IEEE J. Solid State Circuits Hadar Dagan, Aviv Shapira, Adam Teman, Anatoli Mordakhay, Samuel Jameson, Evgeny Pikhay, Vladislav Dayan, Yakov Roizin, Eran Socher, Alexander Fish
2014	J	`jnl`	Replica Technique for Adaptive Refresh Timing of Gain-Cell-Embedded DRAM. IEEE Trans. Circuits Syst. II Express Briefs Adam Teman, Pascal Andreas Meinerzhagen, Robert Giterman, Alexander Fish, Andreas Burg
2013	J	`jnl`	A Low-Power DCVSL-Like GIDL-Free Voltage Driver for Low-Cost RFID Nonvolatile Memory. IEEE J. Solid State Circuits Hadar Dagan, Adam Teman, Evgeny Pikhay, Vladislav Dayan, Anatoli Mordakhay, Yakov Roizin, Alexander Fish
2013	J	`jnl`	Functionality and stability analysis of a 400 mV quasi-static RAM (QSRAM) bitcell. Microelectron. J. Adam Teman, Anatoli Mordakhay, Alexander Fish
2012	J	`jnl`	A 40-nm Sub-Threshold 5T SRAM Bit Cell With Improved Read and Write Stability. IEEE Trans. Circuits Syst. II Express Briefs Adam Teman, Anatoli Mordakhay, Janna Mezhibovsky, Alexander Fish
2012	C	`conf`	A GIDL free tunneling gate driver for a low power non-volatile memory array. ISCAS Hadar Dagan, Adam Teman, Alexander Fish, Evgeny Pikhay, Vladislav Dayan, Yakov Roizin
2012	C	`conf`	A low-cost low-power non-volatile memory for RFID applications. ISCAS Hadar Dagan, Adam Teman, Alexander Fish, Evgeny Pikhay, Vladislav Dayan, Yakov Roizin
2012	J	`jnl`	Low-Voltage 96 dB Snapshot CMOS Image Sensor with 4.5 nW Power Dissipation per Pixel. Sensors Arthur Spivak, Adam Teman, Alexander Belenky, Orly Yadid-Pecht, Alexander Fish
2012	C	`conf`	State space modeling for sub-threshold SRAM stability analysis. ISCAS Janna Mezhibovsky, Adam Teman, Alexander Fish
2011	J	`jnl`	A 250 mV 8 kb 40 nm Ultra-Low Power 9T Supply Feedback SRAM (SF-SRAM). IEEE J. Solid State Circuits Adam Teman, Lidor Pergament, Omer Cohen, Alexander Fish
2011	—	`conf`	Low voltage SRAMs and the scalability of the 9T Supply Feedback SRAM. SoCC Janna Mezhibovsky, Adam Teman, Alexander Fish
2009	C	`conf`	Ultra-low Power Subthreshold Flip-flop Design. ISCAS Sagi Fisher, Adam Teman, Dmitry Vaysman, Alexander Gertsman, Orly Yadid-Pecht, Alexander Fish
2008	C	`conf`	Autonomous CMOS image sensor for real time target detection and tracking. ISCAS Adam Teman, Sagi Fisher, Liby Sudakov, Alexander Fish, Orly Yadid-Pecht